p1_twr.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <hwconfig.h>
  9. #include <image.h>
  10. #include <init.h>
  11. #include <net.h>
  12. #include <pci.h>
  13. #include <i2c.h>
  14. #include <asm/processor.h>
  15. #include <asm/mmu.h>
  16. #include <asm/cache.h>
  17. #include <asm/immap_85xx.h>
  18. #include <asm/fsl_pci.h>
  19. #include <fsl_ddr_sdram.h>
  20. #include <asm/io.h>
  21. #include <asm/fsl_law.h>
  22. #include <asm/fsl_lbc.h>
  23. #include <asm/mp.h>
  24. #include <miiphy.h>
  25. #include <linux/libfdt.h>
  26. #include <fdt_support.h>
  27. #include <fsl_mdio.h>
  28. #include <tsec.h>
  29. #include <ioports.h>
  30. #include <asm/fsl_serdes.h>
  31. #include <netdev.h>
  32. #define SYSCLK_64 64000000
  33. #define SYSCLK_66 66666666
  34. unsigned long get_board_sys_clk(ulong dummy)
  35. {
  36. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  37. par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
  38. unsigned int cpdat_val = 0;
  39. /* Set-up up pin muxing based on board switch settings */
  40. cpdat_val = par_io[1].cpdat;
  41. /* Check switch setting for SYSCLK select (PB3) */
  42. if (cpdat_val & 0x10000000)
  43. return SYSCLK_64;
  44. else
  45. return SYSCLK_66;
  46. return 0;
  47. }
  48. #ifdef CONFIG_QE
  49. #define PCA_IOPORT_I2C_ADDR 0x23
  50. #define PCA_IOPORT_OUTPUT_CMD 0x2
  51. #define PCA_IOPORT_CFG_CMD 0x6
  52. const qe_iop_conf_t qe_iop_conf_tab[] = {
  53. #ifdef CONFIG_TWR_P1025
  54. /* GPIO */
  55. {1, 0, 1, 0, 0},
  56. {1, 18, 1, 0, 0},
  57. /* GPIO for switch options */
  58. {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
  59. {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
  60. {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
  61. {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
  62. /* QE_MUX_MDC */
  63. {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
  64. /* QE_MUX_MDIO */
  65. {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
  66. /* UCC_1_MII */
  67. {0, 23, 2, 0, 2}, /* CLK12 */
  68. {0, 24, 2, 0, 1}, /* CLK9 */
  69. {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
  70. {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
  71. {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
  72. {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
  73. {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
  74. {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
  75. {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
  76. {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
  77. {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
  78. {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
  79. {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
  80. {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
  81. {0, 17, 2, 0, 2}, /* ENET1_CRS */
  82. {0, 16, 2, 0, 2}, /* ENET1_COL */
  83. /* UCC_5_RMII */
  84. {1, 11, 2, 0, 1}, /* CLK13 */
  85. {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
  86. {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
  87. {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
  88. {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
  89. {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
  90. {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
  91. {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
  92. /* TDMA - clock option is configured in OS based on board setting */
  93. {1, 23, 2, 0, 2}, /* TDMA_TXD */
  94. {1, 25, 2, 0, 2}, /* TDMA_RXD */
  95. {1, 26, 1, 0, 2}, /* TDMA_SYNC */
  96. #endif
  97. {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
  98. };
  99. #endif
  100. int board_early_init_f(void)
  101. {
  102. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  103. setbits_be32(&gur->pmuxcr,
  104. (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
  105. /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
  106. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
  107. return 0;
  108. }
  109. int checkboard(void)
  110. {
  111. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  112. u8 boot_status;
  113. printf("Board: %s\n", CONFIG_BOARDNAME);
  114. boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
  115. puts("rom_loc: ");
  116. if (boot_status == PORBMSR_ROMLOC_NOR)
  117. puts("nor flash");
  118. else if (boot_status == PORBMSR_ROMLOC_SDHC)
  119. puts("sd");
  120. else
  121. puts("unknown");
  122. puts("\n");
  123. return 0;
  124. }
  125. #ifdef CONFIG_PCI
  126. void pci_init_board(void)
  127. {
  128. fsl_pcie_init_board(0);
  129. }
  130. #endif
  131. int board_early_init_r(void)
  132. {
  133. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  134. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  135. /*
  136. * Remap Boot flash region to caching-inhibited
  137. * so that flash can be erased properly.
  138. */
  139. /* Flush d-cache and invalidate i-cache of any FLASH data */
  140. flush_dcache();
  141. invalidate_icache();
  142. if (flash_esel == -1) {
  143. /* very unlikely unless something is messed up */
  144. puts("Error: Could not find TLB for FLASH BASE\n");
  145. flash_esel = 2; /* give our best effort to continue */
  146. } else {
  147. /* invalidate existing TLB entry for flash */
  148. disable_tlb(flash_esel);
  149. }
  150. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  151. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  152. 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
  153. return 0;
  154. }
  155. int board_eth_init(bd_t *bis)
  156. {
  157. struct fsl_pq_mdio_info mdio_info;
  158. struct tsec_info_struct tsec_info[4];
  159. ccsr_gur_t *gur __attribute__((unused)) =
  160. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  161. int num = 0;
  162. #ifdef CONFIG_TSEC1
  163. SET_STD_TSEC_INFO(tsec_info[num], 1);
  164. num++;
  165. #endif
  166. #ifdef CONFIG_TSEC2
  167. SET_STD_TSEC_INFO(tsec_info[num], 2);
  168. if (is_serdes_configured(SGMII_TSEC2)) {
  169. printf("eTSEC2 is in sgmii mode.\n");
  170. tsec_info[num].flags |= TSEC_SGMII;
  171. }
  172. num++;
  173. #endif
  174. #ifdef CONFIG_TSEC3
  175. SET_STD_TSEC_INFO(tsec_info[num], 3);
  176. num++;
  177. #endif
  178. if (!num) {
  179. printf("No TSECs initialized\n");
  180. return 0;
  181. }
  182. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  183. mdio_info.name = DEFAULT_MII_NAME;
  184. fsl_pq_mdio_init(bis, &mdio_info);
  185. tsec_eth_init(bis, tsec_info, num);
  186. #if defined(CONFIG_UEC_ETH)
  187. /* QE0 and QE3 need to be exposed for UCC1
  188. * and UCC5 Eth mode (in PMUXCR register).
  189. * Currently QE/LBC muxed pins assumed to be
  190. * LBC for U-Boot and PMUXCR updated by OS if required */
  191. uec_standard_init(bis);
  192. #endif
  193. return pci_eth_init(bis);
  194. }
  195. #if defined(CONFIG_QE)
  196. static void fdt_board_fixup_qe_pins(void *blob)
  197. {
  198. int node;
  199. if (!hwconfig("qe")) {
  200. /* For QE and eLBC pins multiplexing,
  201. * When don't use QE function, remove
  202. * qe node from dt blob.
  203. */
  204. node = fdt_path_offset(blob, "/qe");
  205. if (node >= 0)
  206. fdt_del_node(blob, node);
  207. } else {
  208. /* For TWR Peripheral Modules - TWR-SER2
  209. * board only can support Signal Port MII,
  210. * so delete one UEC node when use MII port.
  211. */
  212. if (hwconfig("mii"))
  213. node = fdt_path_offset(blob, "/qe/ucc@2400");
  214. else
  215. node = fdt_path_offset(blob, "/qe/ucc@2000");
  216. if (node >= 0)
  217. fdt_del_node(blob, node);
  218. }
  219. return;
  220. }
  221. #endif
  222. #ifdef CONFIG_OF_BOARD_SETUP
  223. int ft_board_setup(void *blob, bd_t *bd)
  224. {
  225. phys_addr_t base;
  226. phys_size_t size;
  227. ft_cpu_setup(blob, bd);
  228. base = env_get_bootm_low();
  229. size = env_get_bootm_size();
  230. fdt_fixup_memory(blob, (u64)base, (u64)size);
  231. FT_FSL_PCI_SETUP;
  232. #ifdef CONFIG_QE
  233. do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
  234. sizeof("okay"), 0);
  235. #endif
  236. #if defined(CONFIG_TWR_P1025)
  237. fdt_board_fixup_qe_pins(blob);
  238. #endif
  239. fsl_fdt_fixup_dr_usb(blob, bd);
  240. return 0;
  241. }
  242. #endif