p1022ds.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  4. * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  5. * Timur Tabi <timur@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <env.h>
  10. #include <image.h>
  11. #include <init.h>
  12. #include <net.h>
  13. #include <pci.h>
  14. #include <asm/processor.h>
  15. #include <asm/mmu.h>
  16. #include <asm/cache.h>
  17. #include <asm/immap_85xx.h>
  18. #include <asm/fsl_pci.h>
  19. #include <fsl_ddr_sdram.h>
  20. #include <asm/fsl_serdes.h>
  21. #include <asm/io.h>
  22. #include <linux/libfdt.h>
  23. #include <fdt_support.h>
  24. #include <fsl_mdio.h>
  25. #include <tsec.h>
  26. #include <asm/fsl_law.h>
  27. #include <netdev.h>
  28. #include <i2c.h>
  29. #include <hwconfig.h>
  30. #include "../common/ngpixis.h"
  31. int board_early_init_f(void)
  32. {
  33. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  34. /* Set pmuxcr to allow both i2c1 and i2c2 */
  35. setbits_be32(&gur->pmuxcr, 0x1000);
  36. #ifdef CONFIG_SYS_RAMBOOT
  37. setbits_be32(&gur->pmuxcr,
  38. in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
  39. #endif
  40. /* Read back the register to synchronize the write. */
  41. in_be32(&gur->pmuxcr);
  42. /* Set the pin muxing to enable ETSEC2. */
  43. clrbits_be32(&gur->pmuxcr2, 0x001F8000);
  44. /* Enable the SPI */
  45. clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
  46. return 0;
  47. }
  48. int checkboard(void)
  49. {
  50. u8 sw;
  51. printf("Board: P1022DS Sys ID: 0x%02x, "
  52. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  53. in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  54. sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  55. switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
  56. case 0:
  57. printf ("vBank: %u\n", ((sw & 0x30) >> 4));
  58. break;
  59. case 1:
  60. printf ("NAND\n");
  61. break;
  62. case 2:
  63. case 3:
  64. puts ("Promjet\n");
  65. break;
  66. }
  67. return 0;
  68. }
  69. #define CONFIG_TFP410_I2C_ADDR 0x38
  70. /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
  71. #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
  72. #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
  73. /* Route the I2C1 pins to the SSI port instead. */
  74. #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
  75. /* Choose the 12.288Mhz codec reference clock */
  76. #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
  77. /* Choose the 11.2896Mhz codec reference clock */
  78. #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
  79. /* Connect to USB2 */
  80. #define CONFIG_PIXIS_BRDCFG0_USB2 0x10
  81. /* Connect to TFM bus */
  82. #define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
  83. /* Connect to SPI */
  84. #define CONFIG_PIXIS_BRDCFG0_SPI 0x80
  85. int misc_init_r(void)
  86. {
  87. u8 temp;
  88. const char *audclk;
  89. size_t arglen;
  90. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  91. /* For DVI, enable the TFP410 Encoder. */
  92. temp = 0xBF;
  93. if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
  94. return -1;
  95. if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
  96. return -1;
  97. debug("DVI Encoder Read: 0x%02x\n", temp);
  98. temp = 0x10;
  99. if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
  100. return -1;
  101. if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
  102. return -1;
  103. debug("DVI Encoder Read: 0x%02x\n",temp);
  104. /* Enable the USB2 in PMUXCR2 and FGPA */
  105. if (hwconfig("usb2")) {
  106. clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
  107. MPC85xx_PMUXCR2_USB);
  108. setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
  109. }
  110. /* tdm and audio can not enable simultaneous*/
  111. if (hwconfig("tdm") && hwconfig("audclk")){
  112. printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
  113. return -1;
  114. }
  115. /* Enable the TDM in PMUXCR and FGPA */
  116. if (hwconfig("tdm")) {
  117. clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
  118. MPC85xx_PMUXCR_TDM);
  119. setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
  120. /* TDM need some configration option by SPI */
  121. clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
  122. MPC85xx_PMUXCR_SPI);
  123. setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
  124. }
  125. /*
  126. * Enable the reference clock for the WM8776 codec, and route the MUX
  127. * pins for SSI. The default is the 12.288 MHz clock
  128. */
  129. if (hwconfig("audclk")) {
  130. temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
  131. CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
  132. temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
  133. audclk = hwconfig_arg("audclk", &arglen);
  134. /* Check the first two chars only */
  135. if (audclk && (strncmp(audclk, "11", 2) == 0))
  136. temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
  137. else
  138. temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
  139. setbits_8(&pixis->brdcfg1, temp);
  140. }
  141. return 0;
  142. }
  143. /*
  144. * A list of PCI and SATA slots
  145. */
  146. enum slot_id {
  147. SLOT_PCIE1 = 1,
  148. SLOT_PCIE2,
  149. SLOT_PCIE3,
  150. SLOT_PCIE4,
  151. SLOT_PCIE5,
  152. SLOT_SATA1,
  153. SLOT_SATA2
  154. };
  155. /*
  156. * This array maps the slot identifiers to their names on the P1022DS board.
  157. */
  158. static const char *slot_names[] = {
  159. [SLOT_PCIE1] = "Slot 1",
  160. [SLOT_PCIE2] = "Slot 2",
  161. [SLOT_PCIE3] = "Slot 3",
  162. [SLOT_PCIE4] = "Slot 4",
  163. [SLOT_PCIE5] = "Mini-PCIe",
  164. [SLOT_SATA1] = "SATA 1",
  165. [SLOT_SATA2] = "SATA 2",
  166. };
  167. /*
  168. * This array maps a given SERDES configuration and SERDES device to the PCI or
  169. * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
  170. */
  171. static u8 serdes_dev_slot[][SATA2 + 1] = {
  172. [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
  173. [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  174. [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
  175. [PCIE2] = SLOT_PCIE5 },
  176. [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
  177. [PCIE2] = SLOT_PCIE3,
  178. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  179. [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
  180. [PCIE2] = SLOT_PCIE3 },
  181. [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
  182. [PCIE2] = SLOT_PCIE3,
  183. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  184. [0x1c] = { [PCIE1] = SLOT_PCIE1,
  185. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  186. [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
  187. [0x1f] = { [PCIE1] = SLOT_PCIE1 },
  188. };
  189. /*
  190. * Returns the name of the slot to which the PCIe or SATA controller is
  191. * connected
  192. */
  193. const char *board_serdes_name(enum srds_prtcl device)
  194. {
  195. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  196. u32 pordevsr = in_be32(&gur->pordevsr);
  197. unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  198. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  199. enum slot_id slot = serdes_dev_slot[srds_cfg][device];
  200. const char *name = slot_names[slot];
  201. if (name)
  202. return name;
  203. else
  204. return "Nothing";
  205. }
  206. #ifdef CONFIG_PCI
  207. void pci_init_board(void)
  208. {
  209. fsl_pcie_init_board(0);
  210. }
  211. #endif
  212. int board_early_init_r(void)
  213. {
  214. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  215. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  216. /*
  217. * Remap Boot flash + PROMJET region to caching-inhibited
  218. * so that flash can be erased properly.
  219. */
  220. /* Flush d-cache and invalidate i-cache of any FLASH data */
  221. flush_dcache();
  222. invalidate_icache();
  223. if (flash_esel == -1) {
  224. /* very unlikely unless something is messed up */
  225. puts("Error: Could not find TLB for FLASH BASE\n");
  226. flash_esel = 2; /* give our best effort to continue */
  227. } else {
  228. /* invalidate existing TLB entry for flash + promjet */
  229. disable_tlb(flash_esel);
  230. }
  231. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  232. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  233. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  234. return 0;
  235. }
  236. /*
  237. * Initialize on-board and/or PCI Ethernet devices
  238. *
  239. * Returns:
  240. * <0, error
  241. * 0, no ethernet devices found
  242. * >0, number of ethernet devices initialized
  243. */
  244. int board_eth_init(bd_t *bis)
  245. {
  246. struct fsl_pq_mdio_info mdio_info;
  247. struct tsec_info_struct tsec_info[2];
  248. unsigned int num = 0;
  249. #ifdef CONFIG_TSEC1
  250. SET_STD_TSEC_INFO(tsec_info[num], 1);
  251. num++;
  252. #endif
  253. #ifdef CONFIG_TSEC2
  254. SET_STD_TSEC_INFO(tsec_info[num], 2);
  255. num++;
  256. #endif
  257. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  258. mdio_info.name = DEFAULT_MII_NAME;
  259. fsl_pq_mdio_init(bis, &mdio_info);
  260. return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
  261. }
  262. #ifdef CONFIG_OF_BOARD_SETUP
  263. /**
  264. * ft_codec_setup - fix up the clock-frequency property of the codec node
  265. *
  266. * Update the clock-frequency property based on the value of the 'audclk'
  267. * hwconfig option. If audclk is not specified, then don't write anything
  268. * to the device tree, because it means that the codec clock is disabled.
  269. */
  270. static void ft_codec_setup(void *blob, const char *compatible)
  271. {
  272. const char *audclk;
  273. size_t arglen;
  274. u32 freq;
  275. audclk = hwconfig_arg("audclk", &arglen);
  276. if (audclk) {
  277. if (strncmp(audclk, "11", 2) == 0)
  278. freq = 11289600;
  279. else
  280. freq = 12288000;
  281. do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
  282. freq, 1);
  283. }
  284. }
  285. int ft_board_setup(void *blob, bd_t *bd)
  286. {
  287. phys_addr_t base;
  288. phys_size_t size;
  289. ft_cpu_setup(blob, bd);
  290. base = env_get_bootm_low();
  291. size = env_get_bootm_size();
  292. fdt_fixup_memory(blob, (u64)base, (u64)size);
  293. #ifdef CONFIG_HAS_FSL_DR_USB
  294. fsl_fdt_fixup_dr_usb(blob, bd);
  295. #endif
  296. FT_FSL_PCI_SETUP;
  297. #ifdef CONFIG_FSL_SGMII_RISER
  298. fsl_sgmii_riser_fdt_fixup(blob);
  299. #endif
  300. /* Update the WM8776 node's clock frequency property */
  301. ft_codec_setup(blob, "wlf,wm8776");
  302. return 0;
  303. }
  304. #endif