mx6sabresd.c 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. */
  7. #include <image.h>
  8. #include <init.h>
  9. #include <net.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/iomux.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <asm/mach-imx/spi.h>
  15. #include <env.h>
  16. #include <linux/errno.h>
  17. #include <asm/gpio.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <asm/mach-imx/iomux-v3.h>
  20. #include <asm/mach-imx/boot_mode.h>
  21. #include <asm/mach-imx/video.h>
  22. #include <mmc.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <miiphy.h>
  25. #include <asm/arch/mxc_hdmi.h>
  26. #include <asm/arch/crm_regs.h>
  27. #include <asm/io.h>
  28. #include <asm/arch/sys_proto.h>
  29. #include <i2c.h>
  30. #include <input.h>
  31. #include <power/pmic.h>
  32. #include <power/pfuze100_pmic.h>
  33. #include "../common/pfuze.h"
  34. #include <usb.h>
  35. #include <usb/ehci-ci.h>
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  38. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  39. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  40. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  41. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  42. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  43. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  44. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  45. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  46. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  47. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  48. #define I2C_PMIC 1
  49. #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  50. #define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
  51. #define KEY_VOL_UP IMX_GPIO_NR(1, 4)
  52. int dram_init(void)
  53. {
  54. gd->ram_size = imx_ddr_size();
  55. return 0;
  56. }
  57. static iomux_v3_cfg_t const uart1_pads[] = {
  58. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  59. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  60. };
  61. static iomux_v3_cfg_t const usdhc2_pads[] = {
  62. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  63. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  64. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  65. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  66. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  67. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  68. IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  69. IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  70. IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  71. IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  72. IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
  73. };
  74. static iomux_v3_cfg_t const usdhc3_pads[] = {
  75. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  76. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  77. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  78. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  79. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  80. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  81. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  82. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  83. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  84. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  85. IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
  86. };
  87. static iomux_v3_cfg_t const usdhc4_pads[] = {
  88. IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  89. IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  90. IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  91. IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  92. IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  93. IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  94. IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  95. IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  96. IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  97. IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  98. };
  99. static iomux_v3_cfg_t const ecspi1_pads[] = {
  100. IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  101. IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  102. IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  103. IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  104. };
  105. static iomux_v3_cfg_t const rgb_pads[] = {
  106. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
  107. IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  108. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  109. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  110. IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  111. IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  112. IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  113. IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  114. IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  115. IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  116. IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  117. IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  118. IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  119. IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  120. IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  121. IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  122. IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  123. IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  124. IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  125. IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  126. IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  127. IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  128. IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  129. IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  130. IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  131. IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  132. IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  133. IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  134. IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  135. };
  136. static iomux_v3_cfg_t const bl_pads[] = {
  137. IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  138. };
  139. static void enable_backlight(void)
  140. {
  141. SETUP_IOMUX_PADS(bl_pads);
  142. gpio_request(DISP0_PWR_EN, "Display Power Enable");
  143. gpio_direction_output(DISP0_PWR_EN, 1);
  144. }
  145. static void enable_rgb(struct display_info_t const *dev)
  146. {
  147. SETUP_IOMUX_PADS(rgb_pads);
  148. enable_backlight();
  149. }
  150. static void enable_lvds(struct display_info_t const *dev)
  151. {
  152. enable_backlight();
  153. }
  154. static struct i2c_pads_info mx6q_i2c_pad_info1 = {
  155. .scl = {
  156. .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  157. .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  158. .gp = IMX_GPIO_NR(4, 12)
  159. },
  160. .sda = {
  161. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  162. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  163. .gp = IMX_GPIO_NR(4, 13)
  164. }
  165. };
  166. static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
  167. .scl = {
  168. .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  169. .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  170. .gp = IMX_GPIO_NR(4, 12)
  171. },
  172. .sda = {
  173. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  174. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  175. .gp = IMX_GPIO_NR(4, 13)
  176. }
  177. };
  178. static void setup_spi(void)
  179. {
  180. SETUP_IOMUX_PADS(ecspi1_pads);
  181. }
  182. iomux_v3_cfg_t const di0_pads[] = {
  183. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
  184. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
  185. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */
  186. };
  187. static void setup_iomux_uart(void)
  188. {
  189. SETUP_IOMUX_PADS(uart1_pads);
  190. }
  191. #ifdef CONFIG_FSL_ESDHC_IMX
  192. struct fsl_esdhc_cfg usdhc_cfg[3] = {
  193. {USDHC2_BASE_ADDR},
  194. {USDHC3_BASE_ADDR},
  195. {USDHC4_BASE_ADDR},
  196. };
  197. #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
  198. #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
  199. int board_mmc_get_env_dev(int devno)
  200. {
  201. return devno - 1;
  202. }
  203. int board_mmc_getcd(struct mmc *mmc)
  204. {
  205. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  206. int ret = 0;
  207. switch (cfg->esdhc_base) {
  208. case USDHC2_BASE_ADDR:
  209. ret = !gpio_get_value(USDHC2_CD_GPIO);
  210. break;
  211. case USDHC3_BASE_ADDR:
  212. ret = !gpio_get_value(USDHC3_CD_GPIO);
  213. break;
  214. case USDHC4_BASE_ADDR:
  215. ret = 1; /* eMMC/uSDHC4 is always present */
  216. break;
  217. }
  218. return ret;
  219. }
  220. int board_mmc_init(bd_t *bis)
  221. {
  222. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  223. unsigned reg = readl(&psrc->sbmr1) >> 11;
  224. /*
  225. * Upon reading BOOT_CFG register the following map is done:
  226. * Bit 11 and 12 of BOOT_CFG register can determine the current
  227. * mmc port
  228. * 0x1 SD1
  229. * 0x2 SD2
  230. * 0x3 SD4
  231. */
  232. switch (reg & 0x3) {
  233. case 0x1:
  234. SETUP_IOMUX_PADS(usdhc2_pads);
  235. usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
  236. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  237. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  238. break;
  239. case 0x2:
  240. SETUP_IOMUX_PADS(usdhc3_pads);
  241. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  242. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  243. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  244. break;
  245. case 0x3:
  246. SETUP_IOMUX_PADS(usdhc4_pads);
  247. usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
  248. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  249. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  250. break;
  251. }
  252. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  253. }
  254. #endif
  255. static int ar8031_phy_fixup(struct phy_device *phydev)
  256. {
  257. unsigned short val;
  258. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  259. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  260. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  261. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  262. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  263. val &= 0xffe3;
  264. val |= 0x18;
  265. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  266. /* introduce tx clock delay */
  267. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  268. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  269. val |= 0x0100;
  270. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  271. return 0;
  272. }
  273. int board_phy_config(struct phy_device *phydev)
  274. {
  275. ar8031_phy_fixup(phydev);
  276. if (phydev->drv->config)
  277. phydev->drv->config(phydev);
  278. return 0;
  279. }
  280. #if defined(CONFIG_VIDEO_IPUV3)
  281. static void disable_lvds(struct display_info_t const *dev)
  282. {
  283. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  284. int reg = readl(&iomux->gpr[2]);
  285. reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
  286. IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
  287. writel(reg, &iomux->gpr[2]);
  288. }
  289. static void do_enable_hdmi(struct display_info_t const *dev)
  290. {
  291. disable_lvds(dev);
  292. imx_enable_hdmi_phy();
  293. }
  294. struct display_info_t const displays[] = {{
  295. .bus = -1,
  296. .addr = 0,
  297. .pixfmt = IPU_PIX_FMT_RGB666,
  298. .detect = NULL,
  299. .enable = enable_lvds,
  300. .mode = {
  301. .name = "Hannstar-XGA",
  302. .refresh = 60,
  303. .xres = 1024,
  304. .yres = 768,
  305. .pixclock = 15384,
  306. .left_margin = 160,
  307. .right_margin = 24,
  308. .upper_margin = 29,
  309. .lower_margin = 3,
  310. .hsync_len = 136,
  311. .vsync_len = 6,
  312. .sync = FB_SYNC_EXT,
  313. .vmode = FB_VMODE_NONINTERLACED
  314. } }, {
  315. .bus = -1,
  316. .addr = 0,
  317. .pixfmt = IPU_PIX_FMT_RGB24,
  318. .detect = detect_hdmi,
  319. .enable = do_enable_hdmi,
  320. .mode = {
  321. .name = "HDMI",
  322. .refresh = 60,
  323. .xres = 1024,
  324. .yres = 768,
  325. .pixclock = 15384,
  326. .left_margin = 160,
  327. .right_margin = 24,
  328. .upper_margin = 29,
  329. .lower_margin = 3,
  330. .hsync_len = 136,
  331. .vsync_len = 6,
  332. .sync = FB_SYNC_EXT,
  333. .vmode = FB_VMODE_NONINTERLACED
  334. } }, {
  335. .bus = 0,
  336. .addr = 0,
  337. .pixfmt = IPU_PIX_FMT_RGB24,
  338. .detect = NULL,
  339. .enable = enable_rgb,
  340. .mode = {
  341. .name = "SEIKO-WVGA",
  342. .refresh = 60,
  343. .xres = 800,
  344. .yres = 480,
  345. .pixclock = 29850,
  346. .left_margin = 89,
  347. .right_margin = 164,
  348. .upper_margin = 23,
  349. .lower_margin = 10,
  350. .hsync_len = 10,
  351. .vsync_len = 10,
  352. .sync = 0,
  353. .vmode = FB_VMODE_NONINTERLACED
  354. } } };
  355. size_t display_count = ARRAY_SIZE(displays);
  356. static void setup_display(void)
  357. {
  358. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  359. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  360. int reg;
  361. /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
  362. SETUP_IOMUX_PADS(di0_pads);
  363. enable_ipu_clock();
  364. imx_setup_hdmi();
  365. /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
  366. reg = readl(&mxc_ccm->CCGR3);
  367. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
  368. writel(reg, &mxc_ccm->CCGR3);
  369. /* set LDB0, LDB1 clk select to 011/011 */
  370. reg = readl(&mxc_ccm->cs2cdr);
  371. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  372. | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  373. reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  374. | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  375. writel(reg, &mxc_ccm->cs2cdr);
  376. reg = readl(&mxc_ccm->cscmr2);
  377. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
  378. writel(reg, &mxc_ccm->cscmr2);
  379. reg = readl(&mxc_ccm->chsccdr);
  380. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  381. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  382. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  383. << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
  384. writel(reg, &mxc_ccm->chsccdr);
  385. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  386. | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
  387. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  388. | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  389. | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  390. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  391. | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  392. | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
  393. | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
  394. writel(reg, &iomux->gpr[2]);
  395. reg = readl(&iomux->gpr[3]);
  396. reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
  397. | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  398. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  399. << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
  400. writel(reg, &iomux->gpr[3]);
  401. }
  402. #endif /* CONFIG_VIDEO_IPUV3 */
  403. /*
  404. * Do not overwrite the console
  405. * Use always serial for U-Boot console
  406. */
  407. int overwrite_console(void)
  408. {
  409. return 1;
  410. }
  411. #ifdef CONFIG_USB_EHCI_MX6
  412. static void setup_usb(void)
  413. {
  414. /*
  415. * set daisy chain for otg_pin_id on 6q.
  416. * for 6dl, this bit is reserved
  417. */
  418. imx_iomux_set_gpr_register(1, 13, 1, 0);
  419. }
  420. #endif
  421. int board_early_init_f(void)
  422. {
  423. setup_iomux_uart();
  424. return 0;
  425. }
  426. int board_init(void)
  427. {
  428. /* address of boot parameters */
  429. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  430. #ifdef CONFIG_MXC_SPI
  431. setup_spi();
  432. #endif
  433. if (is_mx6dq() || is_mx6dqp())
  434. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
  435. else
  436. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
  437. #if defined(CONFIG_VIDEO_IPUV3)
  438. setup_display();
  439. #endif
  440. #ifdef CONFIG_USB_EHCI_MX6
  441. setup_usb();
  442. #endif
  443. return 0;
  444. }
  445. int power_init_board(void)
  446. {
  447. struct pmic *p;
  448. unsigned int reg;
  449. int ret;
  450. p = pfuze_common_init(I2C_PMIC);
  451. if (!p)
  452. return -ENODEV;
  453. ret = pfuze_mode_init(p, APS_PFM);
  454. if (ret < 0)
  455. return ret;
  456. /* Increase VGEN3 from 2.5 to 2.8V */
  457. pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
  458. reg &= ~LDO_VOL_MASK;
  459. reg |= LDOB_2_80V;
  460. pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
  461. /* Increase VGEN5 from 2.8 to 3V */
  462. pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
  463. reg &= ~LDO_VOL_MASK;
  464. reg |= LDOB_3_00V;
  465. pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
  466. return 0;
  467. }
  468. #ifdef CONFIG_MXC_SPI
  469. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  470. {
  471. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
  472. }
  473. #endif
  474. #ifdef CONFIG_CMD_BMODE
  475. static const struct boot_mode board_boot_modes[] = {
  476. /* 4 bit bus width */
  477. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  478. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  479. /* 8 bit bus width */
  480. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  481. {NULL, 0},
  482. };
  483. #endif
  484. int board_late_init(void)
  485. {
  486. #ifdef CONFIG_CMD_BMODE
  487. add_board_boot_modes(board_boot_modes);
  488. #endif
  489. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  490. env_set("board_name", "SABRESD");
  491. if (is_mx6dqp())
  492. env_set("board_rev", "MX6QP");
  493. else if (is_mx6dq())
  494. env_set("board_rev", "MX6Q");
  495. else if (is_mx6sdl())
  496. env_set("board_rev", "MX6DL");
  497. #endif
  498. return 0;
  499. }
  500. int checkboard(void)
  501. {
  502. puts("Board: MX6-SabreSD\n");
  503. return 0;
  504. }
  505. #ifdef CONFIG_SPL_BUILD
  506. #include <asm/arch/mx6-ddr.h>
  507. #include <spl.h>
  508. #include <linux/libfdt.h>
  509. #ifdef CONFIG_SPL_OS_BOOT
  510. int spl_start_uboot(void)
  511. {
  512. gpio_request(KEY_VOL_UP, "KEY Volume UP");
  513. gpio_direction_input(KEY_VOL_UP);
  514. /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
  515. return gpio_get_value(KEY_VOL_UP);
  516. }
  517. #endif
  518. static void ccgr_init(void)
  519. {
  520. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  521. writel(0x00C03F3F, &ccm->CCGR0);
  522. writel(0x0030FC03, &ccm->CCGR1);
  523. writel(0x0FFFC000, &ccm->CCGR2);
  524. writel(0x3FF00000, &ccm->CCGR3);
  525. writel(0x00FFF300, &ccm->CCGR4);
  526. writel(0x0F0000C3, &ccm->CCGR5);
  527. writel(0x000003FF, &ccm->CCGR6);
  528. }
  529. static int mx6q_dcd_table[] = {
  530. 0x020e0798, 0x000C0000,
  531. 0x020e0758, 0x00000000,
  532. 0x020e0588, 0x00000030,
  533. 0x020e0594, 0x00000030,
  534. 0x020e056c, 0x00000030,
  535. 0x020e0578, 0x00000030,
  536. 0x020e074c, 0x00000030,
  537. 0x020e057c, 0x00000030,
  538. 0x020e058c, 0x00000000,
  539. 0x020e059c, 0x00000030,
  540. 0x020e05a0, 0x00000030,
  541. 0x020e078c, 0x00000030,
  542. 0x020e0750, 0x00020000,
  543. 0x020e05a8, 0x00000030,
  544. 0x020e05b0, 0x00000030,
  545. 0x020e0524, 0x00000030,
  546. 0x020e051c, 0x00000030,
  547. 0x020e0518, 0x00000030,
  548. 0x020e050c, 0x00000030,
  549. 0x020e05b8, 0x00000030,
  550. 0x020e05c0, 0x00000030,
  551. 0x020e0774, 0x00020000,
  552. 0x020e0784, 0x00000030,
  553. 0x020e0788, 0x00000030,
  554. 0x020e0794, 0x00000030,
  555. 0x020e079c, 0x00000030,
  556. 0x020e07a0, 0x00000030,
  557. 0x020e07a4, 0x00000030,
  558. 0x020e07a8, 0x00000030,
  559. 0x020e0748, 0x00000030,
  560. 0x020e05ac, 0x00000030,
  561. 0x020e05b4, 0x00000030,
  562. 0x020e0528, 0x00000030,
  563. 0x020e0520, 0x00000030,
  564. 0x020e0514, 0x00000030,
  565. 0x020e0510, 0x00000030,
  566. 0x020e05bc, 0x00000030,
  567. 0x020e05c4, 0x00000030,
  568. 0x021b0800, 0xa1390003,
  569. 0x021b080c, 0x001F001F,
  570. 0x021b0810, 0x001F001F,
  571. 0x021b480c, 0x001F001F,
  572. 0x021b4810, 0x001F001F,
  573. 0x021b083c, 0x43270338,
  574. 0x021b0840, 0x03200314,
  575. 0x021b483c, 0x431A032F,
  576. 0x021b4840, 0x03200263,
  577. 0x021b0848, 0x4B434748,
  578. 0x021b4848, 0x4445404C,
  579. 0x021b0850, 0x38444542,
  580. 0x021b4850, 0x4935493A,
  581. 0x021b081c, 0x33333333,
  582. 0x021b0820, 0x33333333,
  583. 0x021b0824, 0x33333333,
  584. 0x021b0828, 0x33333333,
  585. 0x021b481c, 0x33333333,
  586. 0x021b4820, 0x33333333,
  587. 0x021b4824, 0x33333333,
  588. 0x021b4828, 0x33333333,
  589. 0x021b08b8, 0x00000800,
  590. 0x021b48b8, 0x00000800,
  591. 0x021b0004, 0x00020036,
  592. 0x021b0008, 0x09444040,
  593. 0x021b000c, 0x555A7975,
  594. 0x021b0010, 0xFF538F64,
  595. 0x021b0014, 0x01FF00DB,
  596. 0x021b0018, 0x00001740,
  597. 0x021b001c, 0x00008000,
  598. 0x021b002c, 0x000026d2,
  599. 0x021b0030, 0x005A1023,
  600. 0x021b0040, 0x00000027,
  601. 0x021b0000, 0x831A0000,
  602. 0x021b001c, 0x04088032,
  603. 0x021b001c, 0x00008033,
  604. 0x021b001c, 0x00048031,
  605. 0x021b001c, 0x09408030,
  606. 0x021b001c, 0x04008040,
  607. 0x021b0020, 0x00005800,
  608. 0x021b0818, 0x00011117,
  609. 0x021b4818, 0x00011117,
  610. 0x021b0004, 0x00025576,
  611. 0x021b0404, 0x00011006,
  612. 0x021b001c, 0x00000000,
  613. };
  614. static int mx6qp_dcd_table[] = {
  615. 0x020e0798, 0x000c0000,
  616. 0x020e0758, 0x00000000,
  617. 0x020e0588, 0x00000030,
  618. 0x020e0594, 0x00000030,
  619. 0x020e056c, 0x00000030,
  620. 0x020e0578, 0x00000030,
  621. 0x020e074c, 0x00000030,
  622. 0x020e057c, 0x00000030,
  623. 0x020e058c, 0x00000000,
  624. 0x020e059c, 0x00000030,
  625. 0x020e05a0, 0x00000030,
  626. 0x020e078c, 0x00000030,
  627. 0x020e0750, 0x00020000,
  628. 0x020e05a8, 0x00000030,
  629. 0x020e05b0, 0x00000030,
  630. 0x020e0524, 0x00000030,
  631. 0x020e051c, 0x00000030,
  632. 0x020e0518, 0x00000030,
  633. 0x020e050c, 0x00000030,
  634. 0x020e05b8, 0x00000030,
  635. 0x020e05c0, 0x00000030,
  636. 0x020e0774, 0x00020000,
  637. 0x020e0784, 0x00000030,
  638. 0x020e0788, 0x00000030,
  639. 0x020e0794, 0x00000030,
  640. 0x020e079c, 0x00000030,
  641. 0x020e07a0, 0x00000030,
  642. 0x020e07a4, 0x00000030,
  643. 0x020e07a8, 0x00000030,
  644. 0x020e0748, 0x00000030,
  645. 0x020e05ac, 0x00000030,
  646. 0x020e05b4, 0x00000030,
  647. 0x020e0528, 0x00000030,
  648. 0x020e0520, 0x00000030,
  649. 0x020e0514, 0x00000030,
  650. 0x020e0510, 0x00000030,
  651. 0x020e05bc, 0x00000030,
  652. 0x020e05c4, 0x00000030,
  653. 0x021b0800, 0xa1390003,
  654. 0x021b080c, 0x001b001e,
  655. 0x021b0810, 0x002e0029,
  656. 0x021b480c, 0x001b002a,
  657. 0x021b4810, 0x0019002c,
  658. 0x021b083c, 0x43240334,
  659. 0x021b0840, 0x0324031a,
  660. 0x021b483c, 0x43340344,
  661. 0x021b4840, 0x03280276,
  662. 0x021b0848, 0x44383A3E,
  663. 0x021b4848, 0x3C3C3846,
  664. 0x021b0850, 0x2e303230,
  665. 0x021b4850, 0x38283E34,
  666. 0x021b081c, 0x33333333,
  667. 0x021b0820, 0x33333333,
  668. 0x021b0824, 0x33333333,
  669. 0x021b0828, 0x33333333,
  670. 0x021b481c, 0x33333333,
  671. 0x021b4820, 0x33333333,
  672. 0x021b4824, 0x33333333,
  673. 0x021b4828, 0x33333333,
  674. 0x021b08c0, 0x24912249,
  675. 0x021b48c0, 0x24914289,
  676. 0x021b08b8, 0x00000800,
  677. 0x021b48b8, 0x00000800,
  678. 0x021b0004, 0x00020036,
  679. 0x021b0008, 0x24444040,
  680. 0x021b000c, 0x555A7955,
  681. 0x021b0010, 0xFF320F64,
  682. 0x021b0014, 0x01ff00db,
  683. 0x021b0018, 0x00001740,
  684. 0x021b001c, 0x00008000,
  685. 0x021b002c, 0x000026d2,
  686. 0x021b0030, 0x005A1023,
  687. 0x021b0040, 0x00000027,
  688. 0x021b0400, 0x14420000,
  689. 0x021b0000, 0x831A0000,
  690. 0x021b0890, 0x00400C58,
  691. 0x00bb0008, 0x00000000,
  692. 0x00bb000c, 0x2891E41A,
  693. 0x00bb0038, 0x00000564,
  694. 0x00bb0014, 0x00000040,
  695. 0x00bb0028, 0x00000020,
  696. 0x00bb002c, 0x00000020,
  697. 0x021b001c, 0x04088032,
  698. 0x021b001c, 0x00008033,
  699. 0x021b001c, 0x00048031,
  700. 0x021b001c, 0x09408030,
  701. 0x021b001c, 0x04008040,
  702. 0x021b0020, 0x00005800,
  703. 0x021b0818, 0x00011117,
  704. 0x021b4818, 0x00011117,
  705. 0x021b0004, 0x00025576,
  706. 0x021b0404, 0x00011006,
  707. 0x021b001c, 0x00000000,
  708. };
  709. static int mx6dl_dcd_table[] = {
  710. 0x020e0774, 0x000C0000,
  711. 0x020e0754, 0x00000000,
  712. 0x020e04ac, 0x00000030,
  713. 0x020e04b0, 0x00000030,
  714. 0x020e0464, 0x00000030,
  715. 0x020e0490, 0x00000030,
  716. 0x020e074c, 0x00000030,
  717. 0x020e0494, 0x00000030,
  718. 0x020e04a0, 0x00000000,
  719. 0x020e04b4, 0x00000030,
  720. 0x020e04b8, 0x00000030,
  721. 0x020e076c, 0x00000030,
  722. 0x020e0750, 0x00020000,
  723. 0x020e04bc, 0x00000030,
  724. 0x020e04c0, 0x00000030,
  725. 0x020e04c4, 0x00000030,
  726. 0x020e04c8, 0x00000030,
  727. 0x020e04cc, 0x00000030,
  728. 0x020e04d0, 0x00000030,
  729. 0x020e04d4, 0x00000030,
  730. 0x020e04d8, 0x00000030,
  731. 0x020e0760, 0x00020000,
  732. 0x020e0764, 0x00000030,
  733. 0x020e0770, 0x00000030,
  734. 0x020e0778, 0x00000030,
  735. 0x020e077c, 0x00000030,
  736. 0x020e0780, 0x00000030,
  737. 0x020e0784, 0x00000030,
  738. 0x020e078c, 0x00000030,
  739. 0x020e0748, 0x00000030,
  740. 0x020e0470, 0x00000030,
  741. 0x020e0474, 0x00000030,
  742. 0x020e0478, 0x00000030,
  743. 0x020e047c, 0x00000030,
  744. 0x020e0480, 0x00000030,
  745. 0x020e0484, 0x00000030,
  746. 0x020e0488, 0x00000030,
  747. 0x020e048c, 0x00000030,
  748. 0x021b0800, 0xa1390003,
  749. 0x021b080c, 0x001F001F,
  750. 0x021b0810, 0x001F001F,
  751. 0x021b480c, 0x001F001F,
  752. 0x021b4810, 0x001F001F,
  753. 0x021b083c, 0x4220021F,
  754. 0x021b0840, 0x0207017E,
  755. 0x021b483c, 0x4201020C,
  756. 0x021b4840, 0x01660172,
  757. 0x021b0848, 0x4A4D4E4D,
  758. 0x021b4848, 0x4A4F5049,
  759. 0x021b0850, 0x3F3C3D31,
  760. 0x021b4850, 0x3238372B,
  761. 0x021b081c, 0x33333333,
  762. 0x021b0820, 0x33333333,
  763. 0x021b0824, 0x33333333,
  764. 0x021b0828, 0x33333333,
  765. 0x021b481c, 0x33333333,
  766. 0x021b4820, 0x33333333,
  767. 0x021b4824, 0x33333333,
  768. 0x021b4828, 0x33333333,
  769. 0x021b08b8, 0x00000800,
  770. 0x021b48b8, 0x00000800,
  771. 0x021b0004, 0x0002002D,
  772. 0x021b0008, 0x00333030,
  773. 0x021b000c, 0x3F435313,
  774. 0x021b0010, 0xB66E8B63,
  775. 0x021b0014, 0x01FF00DB,
  776. 0x021b0018, 0x00001740,
  777. 0x021b001c, 0x00008000,
  778. 0x021b002c, 0x000026d2,
  779. 0x021b0030, 0x00431023,
  780. 0x021b0040, 0x00000027,
  781. 0x021b0000, 0x831A0000,
  782. 0x021b001c, 0x04008032,
  783. 0x021b001c, 0x00008033,
  784. 0x021b001c, 0x00048031,
  785. 0x021b001c, 0x05208030,
  786. 0x021b001c, 0x04008040,
  787. 0x021b0020, 0x00005800,
  788. 0x021b0818, 0x00011117,
  789. 0x021b4818, 0x00011117,
  790. 0x021b0004, 0x0002556D,
  791. 0x021b0404, 0x00011006,
  792. 0x021b001c, 0x00000000,
  793. };
  794. static void ddr_init(int *table, int size)
  795. {
  796. int i;
  797. for (i = 0; i < size / 2 ; i++)
  798. writel(table[2 * i + 1], table[2 * i]);
  799. }
  800. static void spl_dram_init(void)
  801. {
  802. if (is_mx6dq())
  803. ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
  804. else if (is_mx6dqp())
  805. ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
  806. else if (is_mx6sdl())
  807. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  808. }
  809. void board_init_f(ulong dummy)
  810. {
  811. /* DDR initialization */
  812. spl_dram_init();
  813. /* setup AIPS and disable watchdog */
  814. arch_cpu_init();
  815. ccgr_init();
  816. gpr_init();
  817. /* iomux and setup of i2c */
  818. board_early_init_f();
  819. /* setup GP timer */
  820. timer_init();
  821. /* UART clocks enabled and gd valid - init serial console */
  822. preloader_console_init();
  823. /* Clear the BSS. */
  824. memset(__bss_start, 0, __bss_end - __bss_start);
  825. /* load/boot image from boot device */
  826. board_init_r(NULL, 0);
  827. }
  828. #endif
  829. #ifdef CONFIG_SPL_LOAD_FIT
  830. int board_fit_config_name_match(const char *name)
  831. {
  832. if (is_mx6dq()) {
  833. if (!strcmp(name, "imx6q-sabresd"))
  834. return 0;
  835. } else if (is_mx6dqp()) {
  836. if (!strcmp(name, "imx6qp-sabresd"))
  837. return 0;
  838. } else if (is_mx6dl()) {
  839. if (!strcmp(name, "imx6dl-sabresd"))
  840. return 0;
  841. }
  842. return -1;
  843. }
  844. #endif