eth_lx2160ardb.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. *
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <fdt_support.h>
  9. #include <net.h>
  10. #include <netdev.h>
  11. #include <malloc.h>
  12. #include <fsl_mdio.h>
  13. #include <miiphy.h>
  14. #include <phy.h>
  15. #include <fm_eth.h>
  16. #include <asm/io.h>
  17. #include <exports.h>
  18. #include <asm/arch/fsl_serdes.h>
  19. #include <fsl-mc/fsl_mc.h>
  20. #include <fsl-mc/ldpaa_wriop.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
  23. {
  24. int phy_reg;
  25. u32 phy_id;
  26. phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
  27. phy_id = (phy_reg & 0xffff) << 16;
  28. phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
  29. phy_id |= (phy_reg & 0xffff);
  30. if (phy_id == PHY_UID_IN112525_S03)
  31. return true;
  32. else
  33. return false;
  34. }
  35. int board_eth_init(bd_t *bis)
  36. {
  37. #if defined(CONFIG_FSL_MC_ENET)
  38. struct memac_mdio_info mdio_info;
  39. struct memac_mdio_controller *reg;
  40. int i, interface;
  41. struct mii_dev *dev;
  42. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  43. u32 srds_s1;
  44. srds_s1 = in_le32(&gur->rcwsr[28]) &
  45. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  46. srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  47. reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  48. mdio_info.regs = reg;
  49. mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  50. /* Register the EMI 1 */
  51. fm_memac_mdio_init(bis, &mdio_info);
  52. reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  53. mdio_info.regs = reg;
  54. mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  55. /* Register the EMI 2 */
  56. fm_memac_mdio_init(bis, &mdio_info);
  57. dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  58. switch (srds_s1) {
  59. case 19:
  60. wriop_set_phy_address(WRIOP1_DPMAC2, 0,
  61. CORTINA_PHY_ADDR1);
  62. wriop_set_phy_address(WRIOP1_DPMAC3, 0,
  63. AQR107_PHY_ADDR1);
  64. wriop_set_phy_address(WRIOP1_DPMAC4, 0,
  65. AQR107_PHY_ADDR2);
  66. if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
  67. wriop_set_phy_address(WRIOP1_DPMAC5, 0,
  68. INPHI_PHY_ADDR1);
  69. wriop_set_phy_address(WRIOP1_DPMAC6, 0,
  70. INPHI_PHY_ADDR1);
  71. }
  72. wriop_set_phy_address(WRIOP1_DPMAC17, 0,
  73. RGMII_PHY_ADDR1);
  74. wriop_set_phy_address(WRIOP1_DPMAC18, 0,
  75. RGMII_PHY_ADDR2);
  76. break;
  77. case 18:
  78. wriop_set_phy_address(WRIOP1_DPMAC7, 0,
  79. CORTINA_PHY_ADDR1);
  80. wriop_set_phy_address(WRIOP1_DPMAC8, 0,
  81. CORTINA_PHY_ADDR1);
  82. wriop_set_phy_address(WRIOP1_DPMAC9, 0,
  83. CORTINA_PHY_ADDR1);
  84. wriop_set_phy_address(WRIOP1_DPMAC10, 0,
  85. CORTINA_PHY_ADDR1);
  86. wriop_set_phy_address(WRIOP1_DPMAC3, 0,
  87. AQR107_PHY_ADDR1);
  88. wriop_set_phy_address(WRIOP1_DPMAC4, 0,
  89. AQR107_PHY_ADDR2);
  90. if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
  91. wriop_set_phy_address(WRIOP1_DPMAC5, 0,
  92. INPHI_PHY_ADDR1);
  93. wriop_set_phy_address(WRIOP1_DPMAC6, 0,
  94. INPHI_PHY_ADDR1);
  95. }
  96. wriop_set_phy_address(WRIOP1_DPMAC17, 0,
  97. RGMII_PHY_ADDR1);
  98. wriop_set_phy_address(WRIOP1_DPMAC18, 0,
  99. RGMII_PHY_ADDR2);
  100. break;
  101. default:
  102. printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
  103. srds_s1);
  104. goto next;
  105. }
  106. for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
  107. interface = wriop_get_enet_if(i);
  108. switch (interface) {
  109. case PHY_INTERFACE_MODE_XGMII:
  110. dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
  111. wriop_set_mdio(i, dev);
  112. break;
  113. case PHY_INTERFACE_MODE_25G_AUI:
  114. dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  115. wriop_set_mdio(i, dev);
  116. break;
  117. case PHY_INTERFACE_MODE_XLAUI:
  118. dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
  119. wriop_set_mdio(i, dev);
  120. break;
  121. default:
  122. break;
  123. }
  124. }
  125. for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
  126. interface = wriop_get_enet_if(i);
  127. switch (interface) {
  128. case PHY_INTERFACE_MODE_RGMII:
  129. case PHY_INTERFACE_MODE_RGMII_ID:
  130. dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
  131. wriop_set_mdio(i, dev);
  132. break;
  133. default:
  134. break;
  135. }
  136. }
  137. next:
  138. cpu_eth_init(bis);
  139. #endif /* CONFIG_FSL_MC_ENET */
  140. #ifdef CONFIG_PHY_AQUANTIA
  141. /*
  142. * Export functions to be used by AQ firmware
  143. * upload application
  144. */
  145. gd->jt->strcpy = strcpy;
  146. gd->jt->mdelay = mdelay;
  147. gd->jt->mdio_get_current_dev = mdio_get_current_dev;
  148. gd->jt->phy_find_by_mask = phy_find_by_mask;
  149. gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
  150. gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
  151. #endif
  152. return pci_eth_init(bis);
  153. }
  154. #if defined(CONFIG_RESET_PHY_R)
  155. void reset_phy(void)
  156. {
  157. #if defined(CONFIG_FSL_MC_ENET)
  158. mc_env_boot();
  159. #endif
  160. }
  161. #endif /* CONFIG_RESET_PHY_R */
  162. int fdt_fixup_board_phy(void *fdt)
  163. {
  164. int mdio_offset;
  165. int ret;
  166. struct mii_dev *dev;
  167. ret = 0;
  168. dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  169. if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
  170. mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
  171. if (mdio_offset < 0)
  172. mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
  173. if (mdio_offset < 0) {
  174. printf("mdio@0x8B9700 node not found in dts\n");
  175. return mdio_offset;
  176. }
  177. ret = fdt_setprop_string(fdt, mdio_offset, "status",
  178. "disabled");
  179. if (ret) {
  180. printf("Could not set disable mdio@0x8B97000 %s\n",
  181. fdt_strerror(ret));
  182. return ret;
  183. }
  184. }
  185. return ret;
  186. }