eth_lx2160aqds.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018-2020 NXP
  4. *
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <fdt_support.h>
  9. #include <hwconfig.h>
  10. #include <command.h>
  11. #include <net.h>
  12. #include <netdev.h>
  13. #include <malloc.h>
  14. #include <fsl_mdio.h>
  15. #include <miiphy.h>
  16. #include <phy.h>
  17. #include <fm_eth.h>
  18. #include <asm/io.h>
  19. #include <exports.h>
  20. #include <asm/arch/fsl_serdes.h>
  21. #include <fsl-mc/fsl_mc.h>
  22. #include <fsl-mc/ldpaa_wriop.h>
  23. #include <linux/libfdt.h>
  24. #include "../common/qixis.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #define EMI_NONE 0
  27. #define EMI1 1 /* Mdio Bus 1 */
  28. #define EMI2 2 /* Mdio Bus 2 */
  29. #if defined(CONFIG_FSL_MC_ENET)
  30. enum io_slot {
  31. IO_SLOT_NONE = 0,
  32. IO_SLOT_1,
  33. IO_SLOT_2,
  34. IO_SLOT_3,
  35. IO_SLOT_4,
  36. IO_SLOT_5,
  37. IO_SLOT_6,
  38. IO_SLOT_7,
  39. IO_SLOT_8,
  40. EMI1_RGMII1,
  41. EMI1_RGMII2,
  42. IO_SLOT_MAX
  43. };
  44. struct lx2160a_qds_mdio {
  45. enum io_slot ioslot : 4;
  46. u8 realbusnum : 4;
  47. struct mii_dev *realbus;
  48. };
  49. /* structure explaining the phy configuration on 8 lanes of a serdes*/
  50. struct serdes_phy_config {
  51. u8 serdes; /* serdes protocol */
  52. struct phy_config {
  53. u8 dpmacid;
  54. /* -1 terminated array */
  55. int phy_address[WRIOP_MAX_PHY_NUM + 1];
  56. u8 mdio_bus;
  57. enum io_slot ioslot;
  58. } phy_config[SRDS_MAX_LANES];
  59. };
  60. /* Table defining the phy configuration on 8 lanes of a serdes.
  61. * Various assumptions have been made while defining this table.
  62. * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
  63. * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
  64. * And also that this card is connected to IO Slot 1 (could have been connected
  65. * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
  66. * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
  67. * used in serdes1 protocol 19 (could have selected MDIO 2)
  68. * To override these settings "dpmac" environment variable can be used after
  69. * defining "dpmac_override" in hwconfig environment variable.
  70. * This table has limited serdes protocol entries. It can be expanded as per
  71. * requirement.
  72. */
  73. static const struct serdes_phy_config serdes1_phy_config[] = {
  74. {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
  75. EMI1, IO_SLOT_1},
  76. {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
  77. EMI1, IO_SLOT_1},
  78. {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
  79. EMI1, IO_SLOT_1},
  80. {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
  81. EMI1, IO_SLOT_1} } },
  82. {7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
  83. EMI1, IO_SLOT_1},
  84. {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
  85. EMI1, IO_SLOT_1},
  86. {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
  87. EMI1, IO_SLOT_1},
  88. {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
  89. EMI1, IO_SLOT_1},
  90. {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
  91. EMI1, IO_SLOT_2},
  92. {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
  93. EMI1, IO_SLOT_2},
  94. {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
  95. EMI1, IO_SLOT_2},
  96. {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
  97. EMI1, IO_SLOT_2} } },
  98. {8, {} },
  99. {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  100. EMI1, IO_SLOT_1},
  101. {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  102. EMI1, IO_SLOT_2} } },
  103. {14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  104. EMI1, IO_SLOT_1} } },
  105. {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  106. EMI1, IO_SLOT_1},
  107. {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  108. EMI1, IO_SLOT_1} } },
  109. {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  110. EMI1, IO_SLOT_1},
  111. {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  112. EMI1, IO_SLOT_1},
  113. {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  114. EMI1, IO_SLOT_1},
  115. {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  116. EMI1, IO_SLOT_1} } },
  117. {19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
  118. EMI1, IO_SLOT_2},
  119. {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
  120. EMI1, IO_SLOT_1},
  121. {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
  122. EMI1, IO_SLOT_1},
  123. {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  124. EMI1, IO_SLOT_6},
  125. {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  126. EMI1, IO_SLOT_6} } },
  127. {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
  128. EMI1, IO_SLOT_1},
  129. {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
  130. EMI1, IO_SLOT_2} } }
  131. };
  132. static const struct serdes_phy_config serdes2_phy_config[] = {
  133. {2, {} },
  134. {3, {} },
  135. {5, {} },
  136. {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
  137. EMI1, IO_SLOT_7},
  138. {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
  139. EMI1, IO_SLOT_7},
  140. {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
  141. EMI1, IO_SLOT_7},
  142. {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
  143. EMI1, IO_SLOT_8},
  144. {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
  145. EMI1, IO_SLOT_8},
  146. {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
  147. EMI1, IO_SLOT_8} } },
  148. };
  149. static const struct serdes_phy_config serdes3_phy_config[] = {
  150. {2, {} },
  151. {3, {} }
  152. };
  153. static inline
  154. const struct phy_config *get_phy_config(u8 serdes,
  155. const struct serdes_phy_config *table,
  156. u8 table_size)
  157. {
  158. int i;
  159. for (i = 0; i < table_size; i++) {
  160. if (table[i].serdes == serdes)
  161. return table[i].phy_config;
  162. }
  163. return NULL;
  164. }
  165. /* BRDCFG4 controls EMI routing for the board.
  166. * Bits Function
  167. * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
  168. * EMI1 00= On-board PHY #1
  169. * 01= On-board PHY #2
  170. * 10= (reserved)
  171. * 11= Slots 1..8 multiplexer and translator.
  172. * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
  173. * EMI1X 000= Slot #1
  174. * 001= Slot #2
  175. * 010= Slot #3
  176. * 011= Slot #4
  177. * 100= Slot #5
  178. * 101= Slot #6
  179. * 110= Slot #7
  180. * 111= Slot #8
  181. * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
  182. * EMI2 000= Slot #1 (secondary EMI)
  183. * 001= Slot #2 (secondary EMI)
  184. * 010= Slot #3 (secondary EMI)
  185. * 011= Slot #4 (secondary EMI)
  186. * 100= Slot #5 (secondary EMI)
  187. * 101= Slot #6 (secondary EMI)
  188. * 110= Slot #7 (secondary EMI)
  189. * 111= Slot #8 (secondary EMI)
  190. */
  191. static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
  192. {
  193. switch (realbusnum) {
  194. case EMI1:
  195. switch (ioslot) {
  196. case EMI1_RGMII1:
  197. return 0;
  198. case EMI1_RGMII2:
  199. return 0x40;
  200. default:
  201. return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
  202. }
  203. break;
  204. case EMI2:
  205. return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
  206. default:
  207. return -1;
  208. }
  209. }
  210. static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
  211. {
  212. u8 brdcfg4, mux_val, reg;
  213. brdcfg4 = QIXIS_READ(brdcfg[4]);
  214. reg = brdcfg4;
  215. mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
  216. switch (priv->realbusnum) {
  217. case EMI1:
  218. brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
  219. brdcfg4 |= mux_val;
  220. break;
  221. case EMI2:
  222. brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
  223. brdcfg4 |= mux_val;
  224. break;
  225. }
  226. if (brdcfg4 ^ reg)
  227. QIXIS_WRITE(brdcfg[4], brdcfg4);
  228. }
  229. static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
  230. int devad, int regnum)
  231. {
  232. struct lx2160a_qds_mdio *priv = bus->priv;
  233. lx2160a_qds_mux_mdio(priv);
  234. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  235. }
  236. static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  237. int regnum, u16 value)
  238. {
  239. struct lx2160a_qds_mdio *priv = bus->priv;
  240. lx2160a_qds_mux_mdio(priv);
  241. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  242. }
  243. static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
  244. {
  245. struct lx2160a_qds_mdio *priv = bus->priv;
  246. return priv->realbus->reset(priv->realbus);
  247. }
  248. static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
  249. {
  250. struct lx2160a_qds_mdio *pmdio;
  251. struct mii_dev *bus;
  252. /*should be within MDIO_NAME_LEN*/
  253. char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
  254. if (realbusnum == EMI2) {
  255. if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
  256. printf("invalid ioslot %d\n", ioslot);
  257. return NULL;
  258. }
  259. } else if (realbusnum == EMI1) {
  260. if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
  261. printf("invalid ioslot %d\n", ioslot);
  262. return NULL;
  263. }
  264. } else {
  265. printf("not supported real mdio bus %d\n", realbusnum);
  266. return NULL;
  267. }
  268. if (ioslot == EMI1_RGMII1)
  269. strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
  270. else if (ioslot == EMI1_RGMII2)
  271. strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
  272. else
  273. sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
  274. realbusnum, ioslot);
  275. bus = miiphy_get_dev_by_name(dummy_mdio_name);
  276. if (bus)
  277. return bus;
  278. bus = mdio_alloc();
  279. if (!bus) {
  280. printf("Failed to allocate %s bus\n", dummy_mdio_name);
  281. return NULL;
  282. }
  283. pmdio = malloc(sizeof(*pmdio));
  284. if (!pmdio) {
  285. printf("Failed to allocate %s private data\n", dummy_mdio_name);
  286. free(bus);
  287. return NULL;
  288. }
  289. switch (realbusnum) {
  290. case EMI1:
  291. pmdio->realbus =
  292. miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
  293. break;
  294. case EMI2:
  295. pmdio->realbus =
  296. miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  297. break;
  298. }
  299. if (!pmdio->realbus) {
  300. printf("No real mdio bus num %d found\n", realbusnum);
  301. free(bus);
  302. free(pmdio);
  303. return NULL;
  304. }
  305. pmdio->realbusnum = realbusnum;
  306. pmdio->ioslot = ioslot;
  307. bus->read = lx2160a_qds_mdio_read;
  308. bus->write = lx2160a_qds_mdio_write;
  309. bus->reset = lx2160a_qds_mdio_reset;
  310. strcpy(bus->name, dummy_mdio_name);
  311. bus->priv = pmdio;
  312. if (!mdio_register(bus))
  313. return bus;
  314. printf("No bus with name %s\n", dummy_mdio_name);
  315. free(bus);
  316. free(pmdio);
  317. return NULL;
  318. }
  319. static inline void do_phy_config(const struct phy_config *phy_config)
  320. {
  321. struct mii_dev *bus;
  322. int i, phy_num, phy_address;
  323. for (i = 0; i < SRDS_MAX_LANES; i++) {
  324. if (!phy_config[i].dpmacid)
  325. continue;
  326. for (phy_num = 0;
  327. phy_num < ARRAY_SIZE(phy_config[i].phy_address);
  328. phy_num++) {
  329. phy_address = phy_config[i].phy_address[phy_num];
  330. if (phy_address == -1)
  331. break;
  332. wriop_set_phy_address(phy_config[i].dpmacid,
  333. phy_num, phy_address);
  334. }
  335. /*Register the muxing front-ends to the MDIO buses*/
  336. bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
  337. phy_config[i].ioslot);
  338. if (!bus)
  339. printf("could not get bus for mdio %d ioslot %d\n",
  340. phy_config[i].mdio_bus,
  341. phy_config[i].ioslot);
  342. else
  343. wriop_set_mdio(phy_config[i].dpmacid, bus);
  344. }
  345. }
  346. static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
  347. char *env_dpmac)
  348. {
  349. const char *ret;
  350. size_t len;
  351. u8 realbusnum, ioslot;
  352. struct mii_dev *bus;
  353. int phy_num;
  354. char *phystr = "phy00";
  355. /*search phy in dpmac arg*/
  356. for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
  357. sprintf(phystr, "phy%d", phy_num + 1);
  358. ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
  359. if (!ret) {
  360. /*look for phy instead of phy1*/
  361. if (!phy_num)
  362. ret = hwconfig_subarg_f(arg_dpmacid, "phy",
  363. &len, env_dpmac);
  364. if (!ret)
  365. continue;
  366. }
  367. if (len != 4 || strncmp(ret, "0x", 2))
  368. printf("invalid phy format in %s variable.\n"
  369. "specify phy%d for %s in hex format e.g. 0x12\n",
  370. env_dpmac, phy_num + 1, arg_dpmacid);
  371. else
  372. wriop_set_phy_address(dpmac, phy_num,
  373. simple_strtoul(ret, NULL, 16));
  374. }
  375. /*search mdio in dpmac arg*/
  376. ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
  377. if (ret)
  378. realbusnum = *ret - '0';
  379. else
  380. realbusnum = EMI_NONE;
  381. if (realbusnum) {
  382. /*search io in dpmac arg*/
  383. ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
  384. if (ret)
  385. ioslot = *ret - '0';
  386. else
  387. ioslot = IO_SLOT_NONE;
  388. /*Register the muxing front-ends to the MDIO buses*/
  389. bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
  390. if (!bus)
  391. printf("could not get bus for mdio %d ioslot %d\n",
  392. realbusnum, ioslot);
  393. else
  394. wriop_set_mdio(dpmac, bus);
  395. }
  396. }
  397. #endif
  398. int board_eth_init(bd_t *bis)
  399. {
  400. #if defined(CONFIG_FSL_MC_ENET)
  401. struct memac_mdio_info mdio_info;
  402. struct memac_mdio_controller *regs;
  403. int i;
  404. const char *ret;
  405. char *env_dpmac;
  406. char dpmacid[] = "dpmac00", srds[] = "00_00_00";
  407. size_t len;
  408. struct mii_dev *bus;
  409. const struct phy_config *phy_config;
  410. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  411. u32 srds_s1, srds_s2, srds_s3;
  412. srds_s1 = in_le32(&gur->rcwsr[28]) &
  413. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  414. srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  415. srds_s2 = in_le32(&gur->rcwsr[28]) &
  416. FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
  417. srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
  418. srds_s3 = in_le32(&gur->rcwsr[28]) &
  419. FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
  420. srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
  421. sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
  422. regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  423. mdio_info.regs = regs;
  424. mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  425. /*Register the EMI 1*/
  426. fm_memac_mdio_init(bis, &mdio_info);
  427. regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  428. mdio_info.regs = regs;
  429. mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  430. /*Register the EMI 2*/
  431. fm_memac_mdio_init(bis, &mdio_info);
  432. /* "dpmac" environment variable can be used after
  433. * defining "dpmac_override" in hwconfig environment variable.
  434. */
  435. if (hwconfig("dpmac_override")) {
  436. env_dpmac = env_get("dpmac");
  437. if (env_dpmac) {
  438. ret = hwconfig_arg_f("srds", &len, env_dpmac);
  439. if (ret) {
  440. if (strncmp(ret, srds, strlen(srds))) {
  441. printf("SERDES configuration changed.\n"
  442. "previous: %.*s, current: %s.\n"
  443. "update dpmac variable.\n",
  444. (int)len, ret, srds);
  445. }
  446. } else {
  447. printf("SERDES configuration not found.\n"
  448. "Please add srds:%s in dpmac variable\n",
  449. srds);
  450. }
  451. for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
  452. /* Look for dpmac1 to dpmac24(current max) arg
  453. * in dpmac environment variable
  454. */
  455. sprintf(dpmacid, "dpmac%d", i);
  456. ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
  457. if (ret)
  458. do_dpmac_config(i, dpmacid, env_dpmac);
  459. }
  460. } else {
  461. printf("Warning: environment dpmac not found.\n"
  462. "DPAA network interfaces may not work\n");
  463. }
  464. } else {
  465. /*Look for phy config for serdes1 in phy config table*/
  466. phy_config = get_phy_config(srds_s1, serdes1_phy_config,
  467. ARRAY_SIZE(serdes1_phy_config));
  468. if (!phy_config) {
  469. printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
  470. __func__, srds_s1);
  471. } else {
  472. do_phy_config(phy_config);
  473. }
  474. phy_config = get_phy_config(srds_s2, serdes2_phy_config,
  475. ARRAY_SIZE(serdes2_phy_config));
  476. if (!phy_config) {
  477. printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
  478. __func__, srds_s2);
  479. } else {
  480. do_phy_config(phy_config);
  481. }
  482. phy_config = get_phy_config(srds_s3, serdes3_phy_config,
  483. ARRAY_SIZE(serdes3_phy_config));
  484. if (!phy_config) {
  485. printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
  486. __func__, srds_s3);
  487. } else {
  488. do_phy_config(phy_config);
  489. }
  490. }
  491. if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
  492. wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
  493. bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
  494. if (!bus)
  495. printf("could not get bus for RGMII1\n");
  496. else
  497. wriop_set_mdio(WRIOP1_DPMAC17, bus);
  498. }
  499. if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
  500. wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
  501. bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
  502. if (!bus)
  503. printf("could not get bus for RGMII2\n");
  504. else
  505. wriop_set_mdio(WRIOP1_DPMAC18, bus);
  506. }
  507. cpu_eth_init(bis);
  508. #endif /* CONFIG_FMAN_ENET */
  509. #ifdef CONFIG_PHY_AQUANTIA
  510. /*
  511. * Export functions to be used by AQ firmware
  512. * upload application
  513. */
  514. gd->jt->strcpy = strcpy;
  515. gd->jt->mdelay = mdelay;
  516. gd->jt->mdio_get_current_dev = mdio_get_current_dev;
  517. gd->jt->phy_find_by_mask = phy_find_by_mask;
  518. gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
  519. gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
  520. #endif
  521. return pci_eth_init(bis);
  522. }
  523. #if defined(CONFIG_RESET_PHY_R)
  524. void reset_phy(void)
  525. {
  526. #if defined(CONFIG_FSL_MC_ENET)
  527. mc_env_boot();
  528. #endif
  529. }
  530. #endif /* CONFIG_RESET_PHY_R */
  531. #if defined(CONFIG_FSL_MC_ENET)
  532. int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
  533. {
  534. int offset;
  535. int ret;
  536. char dpmac_str[] = "dpmacs@00";
  537. const char *phy_string;
  538. offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
  539. if (offset < 0)
  540. offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
  541. if (offset < 0) {
  542. printf("dpmacs node not found in device tree\n");
  543. return offset;
  544. }
  545. sprintf(dpmac_str, "dpmac@%x", dpmac_id);
  546. debug("dpmac_str = %s\n", dpmac_str);
  547. offset = fdt_subnode_offset(fdt, offset, dpmac_str);
  548. if (offset < 0) {
  549. printf("%s node not found in device tree\n", dpmac_str);
  550. return offset;
  551. }
  552. phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
  553. if (is_backplane_mode(phy_string)) {
  554. /* Backplane KR mode: skip fixups */
  555. printf("Interface %d in backplane KR mode\n", dpmac_id);
  556. return 0;
  557. }
  558. ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
  559. if (ret)
  560. printf("%d@%s %d\n", __LINE__, __func__, ret);
  561. phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
  562. ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
  563. phy_string);
  564. if (ret)
  565. printf("%d@%s %d\n", __LINE__, __func__, ret);
  566. return ret;
  567. }
  568. int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
  569. {
  570. char mdio_ioslot_str[] = "mdio@00";
  571. struct lx2160a_qds_mdio *priv;
  572. u64 reg;
  573. u32 phandle;
  574. int offset, mux_val;
  575. /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
  576. if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
  577. strlen("LX2160A_QDS_MDIO")))
  578. return -1;
  579. /*Get the real MDIO bus num and ioslot info from bus's priv data*/
  580. priv = mii_dev->priv;
  581. debug("real_bus_num = %d, ioslot = %d\n",
  582. priv->realbusnum, priv->ioslot);
  583. if (priv->realbusnum == EMI1)
  584. reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
  585. else
  586. reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
  587. offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
  588. if (offset < 0) {
  589. printf("mdio@%llx node not found in device tree\n", reg);
  590. return offset;
  591. }
  592. phandle = fdt_get_phandle(fdt, offset);
  593. phandle = cpu_to_fdt32(phandle);
  594. offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
  595. &phandle, 4);
  596. if (offset < 0) {
  597. printf("mdio-mux-%d node not found in device tree\n",
  598. priv->realbusnum == EMI1 ? 1 : 2);
  599. return offset;
  600. }
  601. mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
  602. if (priv->realbusnum == EMI1)
  603. mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
  604. else
  605. mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
  606. sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
  607. offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
  608. if (offset < 0) {
  609. printf("%s node not found in device tree\n", mdio_ioslot_str);
  610. return offset;
  611. }
  612. return offset;
  613. }
  614. int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
  615. struct phy_device *phy_dev, int phandle)
  616. {
  617. char phy_node_name[] = "ethernet-phy@00";
  618. char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
  619. int ret;
  620. sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
  621. debug("phy_node_name = %s\n", phy_node_name);
  622. *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
  623. if (*subnodeoffset <= 0) {
  624. printf("Could not add subnode %s inside node %s err = %s\n",
  625. phy_node_name, fdt_get_name(fdt, offset, NULL),
  626. fdt_strerror(*subnodeoffset));
  627. return *subnodeoffset;
  628. }
  629. sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
  630. phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
  631. debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
  632. ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
  633. phy_id_compatible_str);
  634. if (ret) {
  635. printf("%d@%s %d\n", __LINE__, __func__, ret);
  636. goto out;
  637. }
  638. if (phy_dev->is_c45) {
  639. ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
  640. "ethernet-phy-ieee802.3-c45");
  641. if (ret) {
  642. printf("%d@%s %d\n", __LINE__, __func__, ret);
  643. goto out;
  644. }
  645. } else {
  646. ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
  647. "ethernet-phy-ieee802.3-c22");
  648. if (ret) {
  649. printf("%d@%s %d\n", __LINE__, __func__, ret);
  650. goto out;
  651. }
  652. }
  653. ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
  654. if (ret) {
  655. printf("%d@%s %d\n", __LINE__, __func__, ret);
  656. goto out;
  657. }
  658. ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
  659. if (ret) {
  660. printf("%d@%s %d\n", __LINE__, __func__, ret);
  661. goto out;
  662. }
  663. out:
  664. if (ret)
  665. fdt_del_node(fdt, *subnodeoffset);
  666. return ret;
  667. }
  668. int fdt_fixup_board_phy(void *fdt)
  669. {
  670. int fpga_offset, offset, subnodeoffset;
  671. struct mii_dev *mii_dev;
  672. struct list_head *mii_devs, *entry;
  673. int ret, dpmac_id, phandle, i;
  674. struct phy_device *phy_dev;
  675. char ethname[ETH_NAME_LEN];
  676. phy_interface_t phy_iface;
  677. ret = 0;
  678. /* we know FPGA is connected to i2c0, therefore search path directly,
  679. * instead of compatible property, as it saves time
  680. */
  681. fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
  682. if (fpga_offset < 0)
  683. fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
  684. if (fpga_offset < 0) {
  685. printf("i2c@2000000/fpga node not found in device tree\n");
  686. return fpga_offset;
  687. }
  688. phandle = fdt_alloc_phandle(fdt);
  689. mii_devs = mdio_get_list_head();
  690. list_for_each(entry, mii_devs) {
  691. mii_dev = list_entry(entry, struct mii_dev, link);
  692. debug("mii_dev name : %s\n", mii_dev->name);
  693. offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
  694. if (offset < 0)
  695. continue;
  696. // Look for phy devices attached to MDIO bus muxing front end
  697. // and create their entries with compatible being the device id
  698. for (i = 0; i < PHY_MAX_ADDR; i++) {
  699. phy_dev = mii_dev->phymap[i];
  700. if (!phy_dev)
  701. continue;
  702. // TODO: use sscanf instead of loop
  703. dpmac_id = WRIOP1_DPMAC1;
  704. while (dpmac_id < NUM_WRIOP_PORTS) {
  705. phy_iface = wriop_get_enet_if(dpmac_id);
  706. snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
  707. dpmac_id,
  708. phy_string_for_interface(phy_iface));
  709. if (strcmp(ethname, phy_dev->dev->name) == 0)
  710. break;
  711. dpmac_id++;
  712. }
  713. if (dpmac_id == NUM_WRIOP_PORTS)
  714. continue;
  715. ret = fdt_create_phy_node(fdt, offset, i,
  716. &subnodeoffset,
  717. phy_dev, phandle);
  718. if (ret)
  719. break;
  720. ret = fdt_fixup_dpmac_phy_handle(fdt,
  721. dpmac_id, phandle);
  722. if (ret) {
  723. fdt_del_node(fdt, subnodeoffset);
  724. break;
  725. }
  726. /* calculate offset again as new node addition may have
  727. * changed offset;
  728. */
  729. offset = fdt_get_ioslot_offset(fdt, mii_dev,
  730. fpga_offset);
  731. phandle++;
  732. }
  733. if (ret)
  734. break;
  735. }
  736. return ret;
  737. }
  738. #endif // CONFIG_FSL_MC_ENET