eth.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <net.h>
  8. #include <asm/io.h>
  9. #include <netdev.h>
  10. #include <fm_eth.h>
  11. #include <fsl_dtsec.h>
  12. #include <fsl_mdio.h>
  13. #include <malloc.h>
  14. #include "../common/fman.h"
  15. int board_eth_init(bd_t *bis)
  16. {
  17. #ifdef CONFIG_FMAN_ENET
  18. int i;
  19. struct memac_mdio_info dtsec_mdio_info;
  20. struct memac_mdio_info tgec_mdio_info;
  21. struct mii_dev *dev;
  22. u32 srds_s1;
  23. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  24. srds_s1 = in_be32(&gur->rcwsr[4]) &
  25. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  26. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  27. dtsec_mdio_info.regs =
  28. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  29. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  30. /* Register the 1G MDIO bus */
  31. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  32. tgec_mdio_info.regs =
  33. (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  34. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  35. /* Register the 10G MDIO bus */
  36. fm_memac_mdio_init(bis, &tgec_mdio_info);
  37. /* Set the two on-board RGMII PHY address */
  38. fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
  39. fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
  40. /* Set the two on-board SGMII PHY address */
  41. fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
  42. fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
  43. /* Set the on-board AQ PHY address */
  44. fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  45. switch (srds_s1) {
  46. case 0x1133:
  47. break;
  48. default:
  49. printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
  50. srds_s1);
  51. break;
  52. }
  53. dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  54. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
  55. fm_info_set_mdio(i, dev);
  56. /* XFI on lane A, MAC 9 */
  57. dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  58. fm_info_set_mdio(FM1_10GEC1, dev);
  59. cpu_eth_init(bis);
  60. #endif
  61. return pci_eth_init(bis);
  62. }
  63. #ifdef CONFIG_FMAN_ENET
  64. int fdt_update_ethernet_dt(void *blob)
  65. {
  66. u32 srds_s1;
  67. int i, prop;
  68. int offset, nodeoff;
  69. const char *path;
  70. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  71. srds_s1 = in_be32(&gur->rcwsr[4]) &
  72. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  73. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  74. /* Cycle through all aliases */
  75. for (prop = 0; ; prop++) {
  76. const char *name;
  77. /* FDT might have been edited, recompute the offset */
  78. offset = fdt_first_property_offset(blob,
  79. fdt_path_offset(blob,
  80. "/aliases")
  81. );
  82. /* Select property number 'prop' */
  83. for (i = 0; i < prop; i++)
  84. offset = fdt_next_property_offset(blob, offset);
  85. if (offset < 0)
  86. break;
  87. path = fdt_getprop_by_offset(blob, offset, &name, NULL);
  88. nodeoff = fdt_path_offset(blob, path);
  89. switch (srds_s1) {
  90. case 0x1133:
  91. if (!strcmp(name, "ethernet0"))
  92. fdt_status_disabled(blob, nodeoff);
  93. if (!strcmp(name, "ethernet1"))
  94. fdt_status_disabled(blob, nodeoff);
  95. break;
  96. default:
  97. printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n",
  98. __func__, srds_s1);
  99. break;
  100. }
  101. }
  102. return 0;
  103. }
  104. #endif