bsc9132qds.c 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <image.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/processor.h>
  10. #include <asm/mmu.h>
  11. #include <asm/cache.h>
  12. #include <asm/immap_85xx.h>
  13. #include <asm/io.h>
  14. #include <env.h>
  15. #include <miiphy.h>
  16. #include <linux/libfdt.h>
  17. #include <fdt_support.h>
  18. #include <fsl_mdio.h>
  19. #include <tsec.h>
  20. #include <mmc.h>
  21. #include <netdev.h>
  22. #include <fsl_ifc.h>
  23. #include <hwconfig.h>
  24. #include <i2c.h>
  25. #include <fsl_ddr_sdram.h>
  26. #include <jffs2/load_kernel.h>
  27. #include <mtd_node.h>
  28. #include <flash.h>
  29. #ifdef CONFIG_PCI
  30. #include <pci.h>
  31. #include <asm/fsl_pci.h>
  32. #endif
  33. #include "../common/qixis.h"
  34. DECLARE_GLOBAL_DATA_PTR;
  35. int board_early_init_f(void)
  36. {
  37. struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  38. setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  39. return 0;
  40. }
  41. void board_config_serdes_mux(void)
  42. {
  43. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  44. u32 pordevsr = in_be32(&gur->pordevsr);
  45. u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  46. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  47. switch (srds_cfg) {
  48. /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
  49. case 1:
  50. case 2:
  51. case 3:
  52. case 4:
  53. case 5:
  54. case 22:
  55. case 23:
  56. case 24:
  57. case 25:
  58. case 26:
  59. QIXIS_WRITE_I2C(brdcfg[4], 0x03);
  60. break;
  61. /* PEX(1) PEX(2) SGMII1 CPRI 1 */
  62. case 6:
  63. case 7:
  64. case 8:
  65. case 9:
  66. case 10:
  67. case 27:
  68. case 28:
  69. case 29:
  70. case 30:
  71. case 31:
  72. QIXIS_WRITE_I2C(brdcfg[4], 0x01);
  73. break;
  74. /* PEX(1) PEX(2) SGMII1 SGMII2 */
  75. case 11:
  76. case 32:
  77. QIXIS_WRITE_I2C(brdcfg[4], 0x00);
  78. break;
  79. /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
  80. case 12:
  81. case 13:
  82. case 14:
  83. case 15:
  84. case 16:
  85. case 33:
  86. case 34:
  87. case 35:
  88. case 36:
  89. case 37:
  90. QIXIS_WRITE_I2C(brdcfg[4], 0x07);
  91. break;
  92. /* PEX(1) SGMII2 SGMII1 CPRI 1 */
  93. case 17:
  94. case 18:
  95. case 19:
  96. case 20:
  97. case 21:
  98. case 38:
  99. case 39:
  100. case 40:
  101. case 41:
  102. case 42:
  103. QIXIS_WRITE_I2C(brdcfg[4], 0x05);
  104. break;
  105. /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
  106. case 43:
  107. case 44:
  108. case 45:
  109. case 46:
  110. case 47:
  111. QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
  112. break;
  113. default:
  114. break;
  115. }
  116. }
  117. /* Configure DSP DDR controller */
  118. void dsp_ddr_configure(void)
  119. {
  120. /*
  121. *There are separate DDR-controllers for DSP and PowerPC side DDR.
  122. *copy the ddr controller settings from PowerPC side DDR controller
  123. *to the DSP DDR controller as connected DDR memories are similar.
  124. */
  125. struct ccsr_ddr __iomem *pa_ddr =
  126. (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
  127. struct ccsr_ddr temp_ddr;
  128. struct ccsr_ddr __iomem *dsp_ddr =
  129. (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
  130. memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
  131. temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
  132. temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
  133. memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
  134. dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
  135. }
  136. int board_early_init_r(void)
  137. {
  138. #ifdef CONFIG_MTD_NOR_FLASH
  139. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  140. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  141. /*
  142. * Remap Boot flash region to caching-inhibited
  143. * so that flash can be erased properly.
  144. */
  145. /* Flush d-cache and invalidate i-cache of any FLASH data */
  146. flush_dcache();
  147. invalidate_icache();
  148. if (flash_esel == -1) {
  149. /* very unlikely unless something is messed up */
  150. puts("Error: Could not find TLB for FLASH BASE\n");
  151. flash_esel = 2; /* give our best effort to continue */
  152. } else {
  153. /* invalidate existing TLB entry for flash */
  154. disable_tlb(flash_esel);
  155. }
  156. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  157. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  158. 0, flash_esel, BOOKE_PAGESZ_64M, 1);
  159. set_tlb(1, flashbase + 0x4000000,
  160. CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
  161. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  162. 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
  163. #endif
  164. board_config_serdes_mux();
  165. dsp_ddr_configure();
  166. return 0;
  167. }
  168. #ifdef CONFIG_PCI
  169. void pci_init_board(void)
  170. {
  171. fsl_pcie_init_board(0);
  172. }
  173. #endif /* ifdef CONFIG_PCI */
  174. int checkboard(void)
  175. {
  176. struct cpu_type *cpu;
  177. u8 sw;
  178. cpu = gd->arch.cpu;
  179. printf("Board: %sQDS\n", cpu->name);
  180. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
  181. QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
  182. sw = QIXIS_READ(brdcfg[0]);
  183. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  184. printf("IFC chip select:");
  185. switch (sw) {
  186. case 0:
  187. printf("NOR\n");
  188. break;
  189. case 2:
  190. printf("Promjet\n");
  191. break;
  192. case 4:
  193. printf("NAND\n");
  194. break;
  195. default:
  196. printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  197. break;
  198. }
  199. return 0;
  200. }
  201. int board_eth_init(bd_t *bis)
  202. {
  203. #ifdef CONFIG_TSEC_ENET
  204. struct fsl_pq_mdio_info mdio_info;
  205. struct tsec_info_struct tsec_info[4];
  206. int num = 0;
  207. #ifdef CONFIG_TSEC1
  208. SET_STD_TSEC_INFO(tsec_info[num], 1);
  209. num++;
  210. #endif
  211. #ifdef CONFIG_TSEC2
  212. SET_STD_TSEC_INFO(tsec_info[num], 2);
  213. num++;
  214. #endif
  215. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  216. mdio_info.name = DEFAULT_MII_NAME;
  217. fsl_pq_mdio_init(bis, &mdio_info);
  218. tsec_eth_init(bis, tsec_info, num);
  219. #endif
  220. #ifdef CONFIG_PCI
  221. pci_eth_init(bis);
  222. #endif
  223. return 0;
  224. }
  225. #define USBMUX_SEL_MASK 0xc0
  226. #define USBMUX_SEL_UART2 0xc0
  227. #define USBMUX_SEL_USB 0x40
  228. #define SPIMUX_SEL_UART3 0x80
  229. #define GPS_MUX_SEL_GPS 0x40
  230. #define TSEC_1588_CLKIN_MASK 0x03
  231. #define CON_XCVR_REF_CLK 0x00
  232. int misc_init_r(void)
  233. {
  234. u8 val;
  235. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  236. u32 porbmsr = in_be32(&gur->porbmsr);
  237. u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
  238. /*Configure 1588 clock-in source from RF Card*/
  239. val = QIXIS_READ_I2C(brdcfg[5]);
  240. QIXIS_WRITE_I2C(brdcfg[5],
  241. (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
  242. if (hwconfig("uart2") && hwconfig("usb1")) {
  243. printf("UART2 and USB cannot work together on the board\n");
  244. printf("Remove one from hwconfig and reset\n");
  245. } else {
  246. if (hwconfig("uart2")) {
  247. val = QIXIS_READ_I2C(brdcfg[5]);
  248. QIXIS_WRITE_I2C(brdcfg[5],
  249. (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
  250. clrbits_be32(&gur->pmuxcr3,
  251. MPC85xx_PMUXCR3_USB_SEL_MASK);
  252. setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
  253. } else {
  254. /* By default USB should be selected.
  255. * Programming FPGA to select USB. */
  256. val = QIXIS_READ_I2C(brdcfg[5]);
  257. QIXIS_WRITE_I2C(brdcfg[5],
  258. (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
  259. }
  260. }
  261. if (hwconfig("sim")) {
  262. if (romloc == PORBMSR_ROMLOC_NAND_2K ||
  263. romloc == PORBMSR_ROMLOC_NOR ||
  264. romloc == PORBMSR_ROMLOC_SPI) {
  265. val = QIXIS_READ_I2C(brdcfg[3]);
  266. QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
  267. clrbits_be32(&gur->pmuxcr,
  268. MPC85xx_PMUXCR0_SIM_SEL_MASK);
  269. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
  270. }
  271. }
  272. if (hwconfig("uart3")) {
  273. if (romloc == PORBMSR_ROMLOC_NAND_2K ||
  274. romloc == PORBMSR_ROMLOC_NOR ||
  275. romloc == PORBMSR_ROMLOC_SDHC) {
  276. /* UART3 and SPI1 (Flashes) are muxed together */
  277. val = QIXIS_READ_I2C(brdcfg[3]);
  278. QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
  279. clrbits_be32(&gur->pmuxcr3,
  280. MPC85xx_PMUXCR3_UART3_SEL_MASK);
  281. setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
  282. /* MUX to select UART3 connection to J24 header
  283. * or to GPS */
  284. val = QIXIS_READ_I2C(brdcfg[6]);
  285. if (hwconfig("gps"))
  286. QIXIS_WRITE_I2C(brdcfg[6],
  287. (val | GPS_MUX_SEL_GPS));
  288. else
  289. QIXIS_WRITE_I2C(brdcfg[6],
  290. (val & ~(GPS_MUX_SEL_GPS)));
  291. }
  292. }
  293. return 0;
  294. }
  295. void fdt_del_node_compat(void *blob, const char *compatible)
  296. {
  297. int err;
  298. int off = fdt_node_offset_by_compatible(blob, -1, compatible);
  299. if (off < 0) {
  300. printf("WARNING: could not find compatible node %s: %s.\n",
  301. compatible, fdt_strerror(off));
  302. return;
  303. }
  304. err = fdt_del_node(blob, off);
  305. if (err < 0) {
  306. printf("WARNING: could not remove %s: %s.\n",
  307. compatible, fdt_strerror(err));
  308. }
  309. }
  310. #if defined(CONFIG_OF_BOARD_SETUP)
  311. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  312. static const struct node_info nodes[] = {
  313. { "cfi-flash", MTD_DEV_TYPE_NOR, },
  314. { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
  315. };
  316. #endif
  317. int ft_board_setup(void *blob, bd_t *bd)
  318. {
  319. phys_addr_t base;
  320. phys_size_t size;
  321. ft_cpu_setup(blob, bd);
  322. base = env_get_bootm_low();
  323. size = env_get_bootm_size();
  324. #if defined(CONFIG_PCI)
  325. FT_FSL_PCI_SETUP;
  326. #endif
  327. fdt_fixup_memory(blob, (u64)base, (u64)size);
  328. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  329. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  330. #endif
  331. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  332. u32 porbmsr = in_be32(&gur->porbmsr);
  333. u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
  334. if (!(hwconfig("uart2") && hwconfig("usb1"))) {
  335. /* If uart2 is there in hwconfig remove usb node from
  336. * device tree */
  337. if (hwconfig("uart2")) {
  338. /* remove dts usb node */
  339. fdt_del_node_compat(blob, "fsl-usb2-dr");
  340. } else {
  341. fsl_fdt_fixup_dr_usb(blob, bd);
  342. fdt_del_node_and_alias(blob, "serial2");
  343. }
  344. }
  345. if (hwconfig("uart3")) {
  346. if (romloc == PORBMSR_ROMLOC_NAND_2K ||
  347. romloc == PORBMSR_ROMLOC_NOR ||
  348. romloc == PORBMSR_ROMLOC_SDHC)
  349. /* Delete SPI node from the device tree */
  350. fdt_del_node_and_alias(blob, "spi1");
  351. } else
  352. fdt_del_node_and_alias(blob, "serial3");
  353. if (hwconfig("sim")) {
  354. if (romloc == PORBMSR_ROMLOC_NAND_2K ||
  355. romloc == PORBMSR_ROMLOC_NOR ||
  356. romloc == PORBMSR_ROMLOC_SPI) {
  357. /* remove dts sdhc node */
  358. fdt_del_node_compat(blob, "fsl,esdhc");
  359. } else if (romloc == PORBMSR_ROMLOC_SDHC) {
  360. /* remove dts sim node */
  361. fdt_del_node_compat(blob, "fsl,sim-v1.0");
  362. printf("SIM & SDHC can't work together on the board");
  363. printf("\nRemove sim from hwconfig and reset\n");
  364. }
  365. }
  366. return 0;
  367. }
  368. #endif