dh_imx6.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * DHCOM DH-iMX6 PDK board support
  4. *
  5. * Copyright (C) 2017 Marek Vasut <marex@denx.de>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <eeprom.h>
  10. #include <image.h>
  11. #include <init.h>
  12. #include <net.h>
  13. #include <dm/device-internal.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/crm_regs.h>
  16. #include <asm/arch/imx-regs.h>
  17. #include <asm/arch/iomux.h>
  18. #include <asm/arch/mx6-pins.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/gpio.h>
  21. #include <asm/io.h>
  22. #include <asm/mach-imx/boot_mode.h>
  23. #include <asm/mach-imx/iomux-v3.h>
  24. #include <asm/mach-imx/sata.h>
  25. #include <ahci.h>
  26. #include <dwc_ahsata.h>
  27. #include <env.h>
  28. #include <errno.h>
  29. #include <fsl_esdhc_imx.h>
  30. #include <fuse.h>
  31. #include <i2c_eeprom.h>
  32. #include <mmc.h>
  33. #include <usb.h>
  34. #include <usb/ehci-ci.h>
  35. DECLARE_GLOBAL_DATA_PTR;
  36. int dram_init(void)
  37. {
  38. gd->ram_size = imx_ddr_size();
  39. return 0;
  40. }
  41. /*
  42. * Do not overwrite the console
  43. * Use always serial for U-Boot console
  44. */
  45. int overwrite_console(void)
  46. {
  47. return 1;
  48. }
  49. static int setup_fec_clock(void)
  50. {
  51. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  52. /* set gpr1[21] to select anatop clock */
  53. clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
  54. return enable_fec_anatop_clock(0, ENET_50MHZ);
  55. }
  56. #ifdef CONFIG_USB_EHCI_MX6
  57. static void setup_usb(void)
  58. {
  59. /*
  60. * Set daisy chain for otg_pin_id on MX6Q.
  61. * For MX6DL, this bit is reserved.
  62. */
  63. imx_iomux_set_gpr_register(1, 13, 1, 0);
  64. }
  65. int board_usb_phy_mode(int port)
  66. {
  67. if (port == 1)
  68. return USB_INIT_HOST;
  69. else
  70. return USB_INIT_DEVICE;
  71. }
  72. #endif
  73. static int setup_dhcom_mac_from_fuse(void)
  74. {
  75. struct udevice *dev;
  76. ofnode eeprom;
  77. unsigned char enetaddr[6];
  78. int ret;
  79. ret = eth_env_get_enetaddr("ethaddr", enetaddr);
  80. if (ret) /* ethaddr is already set */
  81. return 0;
  82. imx_get_mac_from_fuse(0, enetaddr);
  83. if (is_valid_ethaddr(enetaddr)) {
  84. eth_env_set_enetaddr("ethaddr", enetaddr);
  85. return 0;
  86. }
  87. eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
  88. if (!ofnode_valid(eeprom)) {
  89. printf("Invalid hardware path to EEPROM!\n");
  90. return -ENODEV;
  91. }
  92. ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
  93. if (ret) {
  94. printf("Cannot find EEPROM!\n");
  95. return ret;
  96. }
  97. ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
  98. if (ret) {
  99. printf("Error reading configuration EEPROM!\n");
  100. return ret;
  101. }
  102. if (is_valid_ethaddr(enetaddr))
  103. eth_env_set_enetaddr("ethaddr", enetaddr);
  104. return 0;
  105. }
  106. int board_early_init_f(void)
  107. {
  108. #ifdef CONFIG_USB_EHCI_MX6
  109. setup_usb();
  110. #endif
  111. return 0;
  112. }
  113. int board_init(void)
  114. {
  115. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  116. /* address of boot parameters */
  117. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  118. /* Enable eim_slow clocks */
  119. setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
  120. setup_dhcom_mac_from_fuse();
  121. setup_fec_clock();
  122. return 0;
  123. }
  124. #ifdef CONFIG_CMD_BMODE
  125. static const struct boot_mode board_boot_modes[] = {
  126. /* 4 bit bus width */
  127. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  128. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  129. /* 8 bit bus width */
  130. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  131. {NULL, 0},
  132. };
  133. #endif
  134. #define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
  135. #define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
  136. #define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
  137. static int board_get_hwcode(void)
  138. {
  139. int hw_code;
  140. gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
  141. gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
  142. gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");
  143. gpio_direction_input(HW_CODE_BIT_0);
  144. gpio_direction_input(HW_CODE_BIT_1);
  145. gpio_direction_input(HW_CODE_BIT_2);
  146. /* HW 100 + HW 200 = 00b; HW 300 = 01b */
  147. hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
  148. (gpio_get_value(HW_CODE_BIT_1) << 1) |
  149. gpio_get_value(HW_CODE_BIT_0)) + 2;
  150. return hw_code;
  151. }
  152. int board_late_init(void)
  153. {
  154. u32 hw_code;
  155. char buf[16];
  156. hw_code = board_get_hwcode();
  157. switch (get_cpu_type()) {
  158. case MXC_CPU_MX6SOLO:
  159. snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
  160. break;
  161. case MXC_CPU_MX6DL:
  162. snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
  163. break;
  164. case MXC_CPU_MX6D:
  165. snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
  166. break;
  167. case MXC_CPU_MX6Q:
  168. snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
  169. break;
  170. default:
  171. snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
  172. break;
  173. }
  174. env_set("dhcom", buf);
  175. #ifdef CONFIG_CMD_BMODE
  176. add_board_boot_modes(board_boot_modes);
  177. #endif
  178. return 0;
  179. }
  180. int checkboard(void)
  181. {
  182. puts("Board: DHCOM i.MX6\n");
  183. return 0;
  184. }
  185. #ifdef CONFIG_MULTI_DTB_FIT
  186. int board_fit_config_name_match(const char *name)
  187. {
  188. if (is_mx6dq()) {
  189. if (!strcmp(name, "imx6q-dhcom-pdk2"))
  190. return 0;
  191. } else if (is_mx6sdl()) {
  192. if (!strcmp(name, "imx6dl-dhcom-pdk2"))
  193. return 0;
  194. }
  195. return -1;
  196. }
  197. #endif