tpl.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <debug_uart.h>
  7. #include <dm.h>
  8. #include <hang.h>
  9. #include <image.h>
  10. #include <spl.h>
  11. #include <asm/cpu.h>
  12. #include <asm/mtrr.h>
  13. #include <asm/processor.h>
  14. #include <asm-generic/sections.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. __weak int arch_cpu_init_dm(void)
  17. {
  18. return 0;
  19. }
  20. static int x86_tpl_init(void)
  21. {
  22. int ret;
  23. debug("%s starting\n", __func__);
  24. ret = x86_cpu_init_tpl();
  25. if (ret) {
  26. debug("%s: x86_cpu_init_tpl() failed\n", __func__);
  27. return ret;
  28. }
  29. ret = spl_init();
  30. if (ret) {
  31. debug("%s: spl_init() failed\n", __func__);
  32. return ret;
  33. }
  34. ret = arch_cpu_init();
  35. if (ret) {
  36. debug("%s: arch_cpu_init() failed\n", __func__);
  37. return ret;
  38. }
  39. ret = arch_cpu_init_dm();
  40. if (ret) {
  41. debug("%s: arch_cpu_init_dm() failed\n", __func__);
  42. return ret;
  43. }
  44. preloader_console_init();
  45. return 0;
  46. }
  47. void board_init_f(ulong flags)
  48. {
  49. int ret;
  50. ret = x86_tpl_init();
  51. if (ret) {
  52. debug("Error %d\n", ret);
  53. panic("x86_tpl_init fail");
  54. }
  55. /* Uninit CAR and jump to board_init_f_r() */
  56. board_init_r(gd, 0);
  57. }
  58. void board_init_f_r(void)
  59. {
  60. /* Not used since we never call board_init_f_r_trampoline() */
  61. while (1);
  62. }
  63. u32 spl_boot_device(void)
  64. {
  65. return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT :
  66. BOOT_DEVICE_SPI_MMAP;
  67. }
  68. int spl_start_uboot(void)
  69. {
  70. return 0;
  71. }
  72. void spl_board_announce_boot_device(void)
  73. {
  74. printf("SPI flash");
  75. }
  76. static int spl_board_load_image(struct spl_image_info *spl_image,
  77. struct spl_boot_device *bootdev)
  78. {
  79. spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
  80. spl_image->entry_point = CONFIG_SPL_TEXT_BASE;
  81. spl_image->load_addr = CONFIG_SPL_TEXT_BASE;
  82. spl_image->os = IH_OS_U_BOOT;
  83. spl_image->name = "U-Boot";
  84. debug("Loading to %lx\n", spl_image->load_addr);
  85. return 0;
  86. }
  87. SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
  88. int spl_spi_load_image(void)
  89. {
  90. return -EPERM;
  91. }
  92. void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
  93. {
  94. debug("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point);
  95. jump_to_spl(spl_image->entry_point);
  96. hang();
  97. }
  98. void spl_board_init(void)
  99. {
  100. preloader_console_init();
  101. }
  102. #if !CONFIG_IS_ENABLED(PCI)
  103. /*
  104. * This is a fake PCI bus for TPL when it doesn't have proper PCI. It is enough
  105. * to bind the devices on the PCI bus, some of which have early-regs properties
  106. * providing fixed BARs. Individual drivers program these BARs themselves so
  107. * that they can access the devices. The BARs are allocated statically in the
  108. * device tree.
  109. *
  110. * Once SPL is running it enables PCI properly, but does not auto-assign BARs
  111. * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
  112. * the auto allocation (after relocation).
  113. */
  114. static const struct udevice_id tpl_fake_pci_ids[] = {
  115. { .compatible = "pci-x86" },
  116. { }
  117. };
  118. U_BOOT_DRIVER(pci_x86) = {
  119. .name = "pci_x86",
  120. .id = UCLASS_SIMPLE_BUS,
  121. .of_match = tpl_fake_pci_ids,
  122. };
  123. #endif