rk3399.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <spl.h>
  8. #include <spl_gpio.h>
  9. #include <syscon.h>
  10. #include <asm/armv8/mmu.h>
  11. #include <asm/io.h>
  12. #include <asm/arch-rockchip/bootrom.h>
  13. #include <asm/arch-rockchip/clock.h>
  14. #include <asm/arch-rockchip/gpio.h>
  15. #include <asm/arch-rockchip/grf_rk3399.h>
  16. #include <asm/arch-rockchip/hardware.h>
  17. #include <power/regulator.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define GRF_EMMCCORE_CON11 0xff77f02c
  20. #define GRF_BASE 0xff770000
  21. const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  22. [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
  23. [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
  24. [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
  25. };
  26. static struct mm_region rk3399_mem_map[] = {
  27. {
  28. .virt = 0x0UL,
  29. .phys = 0x0UL,
  30. .size = 0xf8000000UL,
  31. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  32. PTE_BLOCK_INNER_SHARE
  33. }, {
  34. .virt = 0xf8000000UL,
  35. .phys = 0xf8000000UL,
  36. .size = 0x08000000UL,
  37. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  38. PTE_BLOCK_NON_SHARE |
  39. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  40. }, {
  41. /* List terminator */
  42. 0,
  43. }
  44. };
  45. struct mm_region *mem_map = rk3399_mem_map;
  46. #ifdef CONFIG_SPL_BUILD
  47. #define TIMER_END_COUNT_L 0x00
  48. #define TIMER_END_COUNT_H 0x04
  49. #define TIMER_INIT_COUNT_L 0x10
  50. #define TIMER_INIT_COUNT_H 0x14
  51. #define TIMER_CONTROL_REG 0x1c
  52. #define TIMER_EN 0x1
  53. #define TIMER_FMODE BIT(0)
  54. #define TIMER_RMODE BIT(1)
  55. void rockchip_stimer_init(void)
  56. {
  57. /* If Timer already enabled, don't re-init it */
  58. u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
  59. if (reg & TIMER_EN)
  60. return;
  61. writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
  62. writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
  63. writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
  64. writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
  65. writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
  66. TIMER_CONTROL_REG);
  67. }
  68. #endif
  69. int arch_cpu_init(void)
  70. {
  71. #ifdef CONFIG_SPL_BUILD
  72. struct rk3399_pmusgrf_regs *sgrf;
  73. struct rk3399_grf_regs *grf;
  74. /*
  75. * Disable DDR and SRAM security regions.
  76. *
  77. * As we are entered from the BootROM, the region from
  78. * 0x0 through 0xfffff (i.e. the first MB of memory) will
  79. * be protected. This will cause issues with the DW_MMC
  80. * driver, which tries to DMA from/to the stack (likely)
  81. * located in this range.
  82. */
  83. sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
  84. rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
  85. rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
  86. /* eMMC clock generator: disable the clock multipilier */
  87. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  88. rk_clrreg(&grf->emmccore_con[11], 0x0ff);
  89. #endif
  90. return 0;
  91. }
  92. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  93. void board_debug_uart_init(void)
  94. {
  95. #define GRF_BASE 0xff770000
  96. #define GPIO0_BASE 0xff720000
  97. #define PMUGRF_BASE 0xff320000
  98. struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  99. #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
  100. struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
  101. struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
  102. #endif
  103. #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  104. /* Enable early UART0 on the RK3399 */
  105. rk_clrsetreg(&grf->gpio2c_iomux,
  106. GRF_GPIO2C0_SEL_MASK,
  107. GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
  108. rk_clrsetreg(&grf->gpio2c_iomux,
  109. GRF_GPIO2C1_SEL_MASK,
  110. GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
  111. #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
  112. /* Enable early UART3 on the RK3399 */
  113. rk_clrsetreg(&grf->gpio3b_iomux,
  114. GRF_GPIO3B6_SEL_MASK,
  115. GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
  116. rk_clrsetreg(&grf->gpio3b_iomux,
  117. GRF_GPIO3B7_SEL_MASK,
  118. GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
  119. #else
  120. # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
  121. rk_setreg(&grf->io_vsel, 1 << 0);
  122. /*
  123. * Let's enable these power rails here, we are already running the SPI
  124. * Flash based code.
  125. */
  126. spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
  127. spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
  128. spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
  129. spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
  130. #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
  131. /* Enable early UART2 channel C on the RK3399 */
  132. rk_clrsetreg(&grf->gpio4c_iomux,
  133. GRF_GPIO4C3_SEL_MASK,
  134. GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
  135. rk_clrsetreg(&grf->gpio4c_iomux,
  136. GRF_GPIO4C4_SEL_MASK,
  137. GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
  138. /* Set channel C as UART2 input */
  139. rk_clrsetreg(&grf->soc_con7,
  140. GRF_UART_DBG_SEL_MASK,
  141. GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
  142. #endif
  143. }
  144. #endif
  145. #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
  146. const char *spl_decode_boot_device(u32 boot_device)
  147. {
  148. int i;
  149. static const struct {
  150. u32 boot_device;
  151. const char *ofpath;
  152. } spl_boot_devices_tbl[] = {
  153. { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
  154. { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
  155. { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
  156. };
  157. for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
  158. if (spl_boot_devices_tbl[i].boot_device == boot_device)
  159. return spl_boot_devices_tbl[i].ofpath;
  160. return NULL;
  161. }
  162. void spl_perform_fixups(struct spl_image_info *spl_image)
  163. {
  164. void *blob = spl_image->fdt_addr;
  165. const char *boot_ofpath;
  166. int chosen;
  167. /*
  168. * Inject the ofpath of the device the full U-Boot (or Linux in
  169. * Falcon-mode) was booted from into the FDT, if a FDT has been
  170. * loaded at the same time.
  171. */
  172. if (!blob)
  173. return;
  174. boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
  175. if (!boot_ofpath) {
  176. pr_err("%s: could not map boot_device to ofpath\n", __func__);
  177. return;
  178. }
  179. chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
  180. if (chosen < 0) {
  181. pr_err("%s: could not find/create '/chosen'\n", __func__);
  182. return;
  183. }
  184. fdt_setprop_string(blob, chosen,
  185. "u-boot,spl-boot-device", boot_ofpath);
  186. }
  187. #if defined(SPL_GPIO_SUPPORT)
  188. static void rk3399_force_power_on_reset(void)
  189. {
  190. ofnode node;
  191. struct gpio_desc sysreset_gpio;
  192. debug("%s: trying to force a power-on reset\n", __func__);
  193. node = ofnode_path("/config");
  194. if (!ofnode_valid(node)) {
  195. debug("%s: no /config node?\n", __func__);
  196. return;
  197. }
  198. if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
  199. &sysreset_gpio, GPIOD_IS_OUT)) {
  200. debug("%s: could not find a /config/sysreset-gpio\n", __func__);
  201. return;
  202. }
  203. dm_gpio_set_value(&sysreset_gpio, 1);
  204. }
  205. #endif
  206. void spl_board_init(void)
  207. {
  208. #if defined(SPL_GPIO_SUPPORT)
  209. struct rockchip_cru *cru = rockchip_get_cru();
  210. /*
  211. * The RK3399 resets only 'almost all logic' (see also in the TRM
  212. * "3.9.4 Global software reset"), when issuing a software reset.
  213. * This may cause issues during boot-up for some configurations of
  214. * the application software stack.
  215. *
  216. * To work around this, we test whether the last reset reason was
  217. * a power-on reset and (if not) issue an overtemp-reset to reset
  218. * the entire module.
  219. *
  220. * While this was previously fixed by modifying the various places
  221. * that could generate a software reset (e.g. U-Boot's sysreset
  222. * driver, the ATF or Linux), we now have it here to ensure that
  223. * we no longer have to track this through the various components.
  224. */
  225. if (cru->glb_rst_st != 0)
  226. rk3399_force_power_on_reset();
  227. #endif
  228. #if defined(SPL_DM_REGULATOR)
  229. /*
  230. * Turning the eMMC and SPI back on (if disabled via the Qseven
  231. * BIOS_ENABLE) signal is done through a always-on regulator).
  232. */
  233. if (regulators_enable_boot_on(false))
  234. debug("%s: Cannot enable boot on regulator\n", __func__);
  235. #endif
  236. }
  237. #endif