common.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * K3: Common Architecture initialization
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <image.h>
  11. #include <spl.h>
  12. #include "common.h"
  13. #include <dm.h>
  14. #include <remoteproc.h>
  15. #include <asm/cache.h>
  16. #include <linux/soc/ti/ti_sci_protocol.h>
  17. #include <fdt_support.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/hardware.h>
  20. #include <asm/io.h>
  21. #include <fs_loader.h>
  22. #include <fs.h>
  23. #include <env.h>
  24. #include <elf.h>
  25. struct ti_sci_handle *get_ti_sci_handle(void)
  26. {
  27. struct udevice *dev;
  28. int ret;
  29. ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
  30. DM_GET_DRIVER(ti_sci), &dev);
  31. if (ret)
  32. panic("Failed to get SYSFW (%d)\n", ret);
  33. return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
  34. }
  35. void k3_sysfw_print_ver(void)
  36. {
  37. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  38. char fw_desc[sizeof(ti_sci->version.firmware_description) + 1];
  39. /*
  40. * Output System Firmware version info. Note that since the
  41. * 'firmware_description' field is not guaranteed to be zero-
  42. * terminated we manually add a \0 terminator if needed. Further
  43. * note that we intentionally no longer rely on the extended
  44. * printf() formatter '%.*s' to not having to require a more
  45. * full-featured printf() implementation.
  46. */
  47. strncpy(fw_desc, ti_sci->version.firmware_description,
  48. sizeof(ti_sci->version.firmware_description));
  49. fw_desc[sizeof(fw_desc) - 1] = '\0';
  50. printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
  51. ti_sci->version.abi_major, ti_sci->version.abi_minor,
  52. ti_sci->version.firmware_revision, fw_desc);
  53. }
  54. DECLARE_GLOBAL_DATA_PTR;
  55. #ifdef CONFIG_K3_EARLY_CONS
  56. int early_console_init(void)
  57. {
  58. struct udevice *dev;
  59. int ret;
  60. gd->baudrate = CONFIG_BAUDRATE;
  61. ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
  62. &dev);
  63. if (ret) {
  64. printf("Error getting serial dev for early console! (%d)\n",
  65. ret);
  66. return ret;
  67. }
  68. gd->cur_serial_dev = dev;
  69. gd->flags |= GD_FLG_SERIAL_READY;
  70. gd->have_console = 1;
  71. return 0;
  72. }
  73. #endif
  74. #ifdef CONFIG_SYS_K3_SPL_ATF
  75. void init_env(void)
  76. {
  77. #ifdef CONFIG_SPL_ENV_SUPPORT
  78. char *part;
  79. env_init();
  80. env_relocate();
  81. switch (spl_boot_device()) {
  82. case BOOT_DEVICE_MMC2:
  83. part = env_get("bootpart");
  84. env_set("storage_interface", "mmc");
  85. env_set("fw_dev_part", part);
  86. break;
  87. case BOOT_DEVICE_SPI:
  88. env_set("storage_interface", "ubi");
  89. env_set("fw_ubi_mtdpart", "UBI");
  90. env_set("fw_ubi_volume", "UBI0");
  91. break;
  92. default:
  93. printf("%s from device %u not supported!\n",
  94. __func__, spl_boot_device());
  95. return;
  96. }
  97. #endif
  98. }
  99. #ifdef CONFIG_FS_LOADER
  100. int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
  101. {
  102. struct udevice *fsdev;
  103. char *name = NULL;
  104. int size = 0;
  105. *loadaddr = 0;
  106. #ifdef CONFIG_SPL_ENV_SUPPORT
  107. switch (spl_boot_device()) {
  108. case BOOT_DEVICE_MMC2:
  109. name = env_get(name_fw);
  110. *loadaddr = env_get_hex(name_loadaddr, *loadaddr);
  111. break;
  112. default:
  113. printf("Loading rproc fw image from device %u not supported!\n",
  114. spl_boot_device());
  115. return 0;
  116. }
  117. #endif
  118. if (!*loadaddr)
  119. return 0;
  120. if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
  121. size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr,
  122. 0, 0);
  123. }
  124. return size;
  125. }
  126. #else
  127. int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
  128. {
  129. return 0;
  130. }
  131. #endif
  132. __weak void start_non_linux_remote_cores(void)
  133. {
  134. }
  135. void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
  136. {
  137. typedef void __noreturn (*image_entry_noargs_t)(void);
  138. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  139. u32 loadaddr = 0;
  140. int ret, size;
  141. /* Release all the exclusive devices held by SPL before starting ATF */
  142. ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
  143. ret = rproc_init();
  144. if (ret)
  145. panic("rproc failed to be initialized (%d)\n", ret);
  146. init_env();
  147. start_non_linux_remote_cores();
  148. size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
  149. &loadaddr);
  150. /*
  151. * It is assumed that remoteproc device 1 is the corresponding
  152. * Cortex-A core which runs ATF. Make sure DT reflects the same.
  153. */
  154. ret = rproc_load(1, spl_image->entry_point, 0x200);
  155. if (ret)
  156. panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
  157. /* Add an extra newline to differentiate the ATF logs from SPL */
  158. printf("Starting ATF on ARM64 core...\n\n");
  159. ret = rproc_start(1);
  160. if (ret)
  161. panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
  162. if (!(size > 0 && valid_elf_image(loadaddr))) {
  163. debug("Shutting down...\n");
  164. release_resources_for_core_shutdown();
  165. while (1)
  166. asm volatile("wfe");
  167. }
  168. image_entry_noargs_t image_entry =
  169. (image_entry_noargs_t)load_elf_image_phdr(loadaddr);
  170. image_entry();
  171. }
  172. #endif
  173. #if defined(CONFIG_OF_LIBFDT)
  174. int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
  175. {
  176. u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
  177. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  178. int ret, node, subnode, len, prev_node;
  179. u32 range[4], addr, size;
  180. const fdt32_t *sub_reg;
  181. ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
  182. msmc_size = msmc_end - msmc_start + 1;
  183. debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
  184. msmc_start, msmc_size);
  185. /* find or create "msmc_sram node */
  186. ret = fdt_path_offset(blob, parent_path);
  187. if (ret < 0)
  188. return ret;
  189. node = fdt_find_or_add_subnode(blob, ret, node_name);
  190. if (node < 0)
  191. return node;
  192. ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
  193. if (ret < 0)
  194. return ret;
  195. reg[0] = cpu_to_fdt64(msmc_start);
  196. reg[1] = cpu_to_fdt64(msmc_size);
  197. ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
  198. if (ret < 0)
  199. return ret;
  200. fdt_setprop_cell(blob, node, "#address-cells", 1);
  201. fdt_setprop_cell(blob, node, "#size-cells", 1);
  202. range[0] = 0;
  203. range[1] = cpu_to_fdt32(msmc_start >> 32);
  204. range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
  205. range[3] = cpu_to_fdt32(msmc_size);
  206. ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
  207. if (ret < 0)
  208. return ret;
  209. subnode = fdt_first_subnode(blob, node);
  210. prev_node = 0;
  211. /* Look for invalid subnodes and delete them */
  212. while (subnode >= 0) {
  213. sub_reg = fdt_getprop(blob, subnode, "reg", &len);
  214. addr = fdt_read_number(sub_reg, 1);
  215. sub_reg++;
  216. size = fdt_read_number(sub_reg, 1);
  217. debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
  218. subnode, addr, size);
  219. if (addr + size > msmc_size ||
  220. !strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
  221. !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
  222. fdt_del_node(blob, subnode);
  223. debug("%s: deleting subnode %d\n", __func__, subnode);
  224. if (!prev_node)
  225. subnode = fdt_first_subnode(blob, node);
  226. else
  227. subnode = fdt_next_subnode(blob, prev_node);
  228. } else {
  229. prev_node = subnode;
  230. subnode = fdt_next_subnode(blob, prev_node);
  231. }
  232. }
  233. return 0;
  234. }
  235. int fdt_disable_node(void *blob, char *node_path)
  236. {
  237. int offs;
  238. int ret;
  239. offs = fdt_path_offset(blob, node_path);
  240. if (offs < 0) {
  241. printf("Node %s not found.\n", node_path);
  242. return offs;
  243. }
  244. ret = fdt_setprop_string(blob, offs, "status", "disabled");
  245. if (ret < 0) {
  246. printf("Could not add status property to node %s: %s\n",
  247. node_path, fdt_strerror(ret));
  248. return ret;
  249. }
  250. return 0;
  251. }
  252. #endif
  253. #ifndef CONFIG_SYSRESET
  254. void reset_cpu(ulong ignored)
  255. {
  256. }
  257. #endif
  258. #if defined(CONFIG_DISPLAY_CPUINFO)
  259. int print_cpuinfo(void)
  260. {
  261. u32 soc, rev;
  262. char *name;
  263. soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
  264. JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
  265. rev = (readl(CTRLMMR_WKUP_JTAG_ID) &
  266. JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
  267. printf("SoC: ");
  268. switch (soc) {
  269. case AM65X:
  270. name = "AM65x";
  271. break;
  272. case J721E:
  273. name = "J721E";
  274. break;
  275. default:
  276. name = "Unknown Silicon";
  277. };
  278. printf("%s SR ", name);
  279. switch (rev) {
  280. case REV_PG1_0:
  281. name = "1.0";
  282. break;
  283. case REV_PG2_0:
  284. name = "2.0";
  285. break;
  286. default:
  287. name = "Unknown Revision";
  288. };
  289. printf("%s\n", name);
  290. return 0;
  291. }
  292. #endif
  293. #ifdef CONFIG_ARM64
  294. void board_prep_linux(bootm_headers_t *images)
  295. {
  296. debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
  297. images->os.start, images->os.end);
  298. __asm_flush_dcache_range(images->os.start,
  299. ROUND(images->os.end,
  300. CONFIG_SYS_CACHELINE_SIZE));
  301. }
  302. #endif
  303. #ifdef CONFIG_CPU_V7R
  304. void disable_linefill_optimization(void)
  305. {
  306. u32 actlr;
  307. /*
  308. * On K3 devices there are 2 conditions where R5F can deadlock:
  309. * 1.When software is performing series of store operations to
  310. * cacheable write back/write allocate memory region and later
  311. * on software execute barrier operation (DSB or DMB). R5F may
  312. * hang at the barrier instruction.
  313. * 2.When software is performing a mix of load and store operations
  314. * within a tight loop and store operations are all writing to
  315. * cacheable write back/write allocates memory regions, R5F may
  316. * hang at one of the load instruction.
  317. *
  318. * To avoid the above two conditions disable linefill optimization
  319. * inside Cortex R5F.
  320. */
  321. asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
  322. actlr |= (1 << 13); /* Set DLFO bit */
  323. asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
  324. }
  325. #endif
  326. void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
  327. {
  328. struct ti_sci_msg_fwl_region region;
  329. struct ti_sci_fwl_ops *fwl_ops;
  330. struct ti_sci_handle *ti_sci;
  331. size_t i, j;
  332. ti_sci = get_ti_sci_handle();
  333. fwl_ops = &ti_sci->ops.fwl_ops;
  334. for (i = 0; i < fwl_data_size; i++) {
  335. for (j = 0; j < fwl_data[i].regions; j++) {
  336. region.fwl_id = fwl_data[i].fwl_id;
  337. region.region = j;
  338. region.n_permission_regs = 3;
  339. fwl_ops->get_fwl_region(ti_sci, &region);
  340. if (region.control != 0) {
  341. pr_debug("Attempting to disable firewall %5d (%25s)\n",
  342. region.fwl_id, fwl_data[i].name);
  343. region.control = 0;
  344. if (fwl_ops->set_fwl_region(ti_sci, &region))
  345. pr_err("Could not disable firewall %5d (%25s)\n",
  346. region.fwl_id, fwl_data[i].name);
  347. }
  348. }
  349. }
  350. }