ls1028_ids.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <asm/arch-fsl-layerscape/immap_lsch3.h>
  8. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  9. #include <asm/arch-fsl-layerscape/fsl_portals.h>
  10. struct icid_id_table icid_tbl[] = {
  11. SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
  12. SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
  13. SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
  14. SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
  15. SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
  16. SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
  17. SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
  18. SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
  19. SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
  20. #ifdef CONFIG_FSL_CAAM
  21. SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
  22. SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
  23. SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
  24. SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
  25. SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
  26. SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
  27. SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
  28. SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
  29. SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
  30. SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
  31. #endif
  32. };
  33. int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
  34. /* integrated PCI is handled separately as it's not part of CCSR/SCFG */
  35. #ifdef CONFIG_PCIE_ECAM_GENERIC
  36. #define ECAM_IERB_BASE 0x1f0800000ULL
  37. #define ECAM_IERB_OFFSET_NA -1
  38. #define ECAM_IERB_FUNC_CNT ARRAY_SIZE(ierb_offset)
  39. /* cache related transaction attributes for PCIe functions */
  40. #define ECAM_IERB_MSICAR (ECAM_IERB_BASE + 0xa400)
  41. #define ECAM_IERB_MSICAR_VALUE 0x30
  42. /* offset of IERB config register per PCI function */
  43. static int ierb_offset[] = {
  44. 0x0800,
  45. 0x1800,
  46. 0x2800,
  47. 0x3800,
  48. 0x4800,
  49. 0x5800,
  50. 0x6800,
  51. ECAM_IERB_OFFSET_NA,
  52. 0x0804,
  53. 0x0808,
  54. 0x1804,
  55. 0x1808,
  56. };
  57. /*
  58. * Use a custom function for LS1028A, for now this is the only SoC with IERB
  59. * and we're currently considering reorganizing IERB for future SoCs.
  60. */
  61. void set_ecam_icids(void)
  62. {
  63. int i;
  64. out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
  65. for (i = 0; i < ECAM_IERB_FUNC_CNT; i++) {
  66. if (ierb_offset[i] == ECAM_IERB_OFFSET_NA)
  67. continue;
  68. out_le32(ECAM_IERB_BASE + ierb_offset[i],
  69. FSL_ECAM_STREAM_ID_START + i);
  70. }
  71. }
  72. static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
  73. const char *name, uint32_t idx, u32 val)
  74. {
  75. val = cpu_to_be32(val);
  76. return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
  77. strlen(name),
  78. idx * sizeof(val), &val,
  79. sizeof(val));
  80. }
  81. static int fdt_getprop_len(void *fdt, int nodeoffset, const char *name)
  82. {
  83. int len;
  84. if (fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), &len))
  85. return len;
  86. return 0;
  87. }
  88. void fdt_fixup_ecam(void *blob)
  89. {
  90. int off;
  91. off = fdt_node_offset_by_compatible(blob, 0, "pci-host-ecam-generic");
  92. if (off < 0) {
  93. debug("ECAM node not found\n");
  94. return;
  95. }
  96. if (fdt_getprop_len(blob, off, "msi-map") != 16 ||
  97. fdt_getprop_len(blob, off, "iommu-map") != 16) {
  98. log_err("invalid msi/iommu-map propertly size in ECAM node\n");
  99. return;
  100. }
  101. fdt_setprop_inplace_idx_u32(blob, off, "msi-map", 2,
  102. FSL_ECAM_STREAM_ID_START);
  103. fdt_setprop_inplace_idx_u32(blob, off, "msi-map", 3,
  104. ECAM_IERB_FUNC_CNT);
  105. fdt_setprop_inplace_idx_u32(blob, off, "iommu-map", 2,
  106. FSL_ECAM_STREAM_ID_START);
  107. fdt_setprop_inplace_idx_u32(blob, off, "iommu-map", 3,
  108. ECAM_IERB_FUNC_CNT);
  109. }
  110. #endif /* CONFIG_PCIE_ECAM_GENERIC */