rk3128_common.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. */
  5. #ifndef __CONFIG_RK3128_COMMON_H
  6. #define __CONFIG_RK3128_COMMON_H
  7. #include "rockchip-common.h"
  8. #define CONFIG_SYS_MAXARGS 16
  9. #define CONFIG_BAUDRATE 115200
  10. #define CONFIG_SYS_CBSIZE 1024
  11. #define CONFIG_SKIP_LOWLEVEL_INIT
  12. #define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
  13. #define COUNTER_FREQUENCY 24000000
  14. #define CONFIG_SYS_ARCH_TIMER
  15. #define CONFIG_SYS_HZ_CLOCK 24000000
  16. #define CONFIG_IRAM_BASE 0x10080000
  17. #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
  18. #define CONFIG_SYS_LOAD_ADDR 0x60800800
  19. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
  20. /* RAW SD card / eMMC locations. */
  21. #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
  22. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  23. #define CONFIG_SYS_SDRAM_BASE 0x60000000
  24. #define SDRAM_MAX_SIZE 0x80000000
  25. #define CONFIG_USB_OHCI_NEW
  26. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
  27. #ifndef CONFIG_SPL_BUILD
  28. /* usb mass storage */
  29. #define ENV_MEM_LAYOUT_SETTINGS \
  30. "scriptaddr=0x60500000\0" \
  31. "pxefile_addr_r=0x60600000\0" \
  32. "fdt_addr_r=0x61f00000\0" \
  33. "kernel_addr_r=0x62000000\0" \
  34. "ramdisk_addr_r=0x64000000\0"
  35. #include <config_distro_bootcmd.h>
  36. #define CONFIG_EXTRA_ENV_SETTINGS \
  37. ENV_MEM_LAYOUT_SETTINGS \
  38. "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  39. "partitions=" PARTS_DEFAULT \
  40. BOOTENV
  41. #endif
  42. #endif