x600.h 10 KB

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  1. /*
  2. * (C) Copyright 2009
  3. * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
  4. *
  5. * Copyright (C) 2012 Stefan Roese <sr@denx.de>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * High Level Configuration Options
  13. * (easy to change)
  14. */
  15. #define CONFIG_SPEAR600 /* SPEAr600 SoC */
  16. #define CONFIG_X600 /* on X600 board */
  17. #include <asm/arch/hardware.h>
  18. /* Timer, HZ specific defines */
  19. #define CONFIG_SYS_HZ_CLOCK 8300000
  20. #define CONFIG_SYS_TEXT_BASE 0x00800040
  21. #define CONFIG_SYS_FLASH_BASE 0xf8000000
  22. /* Reserve 8KiB for SPL */
  23. #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
  24. #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
  25. #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
  26. CONFIG_SYS_SPL_LEN)
  27. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  28. #define CONFIG_SYS_MONITOR_LEN 0x60000
  29. #define CONFIG_ENV_IS_IN_FLASH
  30. /* Serial Configuration (PL011) */
  31. #define CONFIG_SYS_SERIAL0 0xD0000000
  32. #define CONFIG_SYS_SERIAL1 0xD0080000
  33. #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
  34. (void *)CONFIG_SYS_SERIAL1 }
  35. #define CONFIG_PL011_SERIAL
  36. #define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
  37. #define CONFIG_CONS_INDEX 0
  38. #define CONFIG_BAUDRATE 115200
  39. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
  40. 57600, 115200 }
  41. #define CONFIG_SYS_LOADS_BAUD_CHANGE
  42. /* NOR FLASH config options */
  43. #define CONFIG_ST_SMI
  44. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  45. #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
  46. #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
  47. #define CONFIG_SYS_MAX_FLASH_SECT 128
  48. #define CONFIG_SYS_FLASH_EMPTY_INFO
  49. #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
  50. #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
  51. /* NAND FLASH config options */
  52. #define CONFIG_NAND_FSMC
  53. #define CONFIG_SYS_NAND_SELF_INIT
  54. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  55. #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
  56. #define CONFIG_MTD_ECC_SOFT
  57. #define CONFIG_SYS_FSMC_NAND_8BIT
  58. #define CONFIG_SYS_NAND_ONFI_DETECTION
  59. /* UBI/UBI config options */
  60. #define CONFIG_MTD_DEVICE
  61. #define CONFIG_MTD_PARTITIONS
  62. #define CONFIG_RBTREE
  63. /* Ethernet config options */
  64. #define CONFIG_MII
  65. #define CONFIG_DESIGNWARE_ETH
  66. #define CONFIG_NET_MULTI
  67. #define CONFIG_PHYLIB
  68. #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
  69. #define CONFIG_PHY_ADDR 0 /* PHY address */
  70. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  71. #define CONFIG_SPEAR_GPIO
  72. /* I2C config options */
  73. #define CONFIG_HARD_I2C
  74. #define CONFIG_DW_I2C
  75. #define CONFIG_SYS_I2C_BASE 0xD0200000
  76. #define CONFIG_SYS_I2C_SPEED 400000
  77. #define CONFIG_SYS_I2C_SLAVE 0x02
  78. #define CONFIG_I2C_CHIPADDRESS 0x50
  79. #define CONFIG_RTC_M41T62 1
  80. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  81. /* FPGA config options */
  82. #define CONFIG_FPGA
  83. #define CONFIG_FPGA_XILINX
  84. #define CONFIG_FPGA_SPARTAN3
  85. #define CONFIG_FPGA_COUNT 1
  86. /*
  87. * Command support defines
  88. */
  89. #define CONFIG_CMD_CACHE
  90. #define CONFIG_CMD_DATE
  91. #define CONFIG_CMD_DHCP
  92. #define CONFIG_CMD_ENV
  93. #define CONFIG_CMD_FPGA
  94. #define CONFIG_CMD_FPGA_LOADMK
  95. #define CONFIG_CMD_GPIO
  96. #define CONFIG_CMD_I2C
  97. #define CONFIG_CMD_MEMORY
  98. #define CONFIG_CMD_MII
  99. #define CONFIG_CMD_MTDPARTS
  100. #define CONFIG_CMD_NAND
  101. #define CONFIG_CMD_NET
  102. #define CONFIG_CMD_PING
  103. #define CONFIG_CMD_RUN
  104. #define CONFIG_CMD_SAVES
  105. #define CONFIG_CMD_UBI
  106. #define CONFIG_CMD_UBIFS
  107. #define CONFIG_LZO
  108. /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  109. #include <config_cmd_default.h>
  110. #define CONFIG_BOOTDELAY 3
  111. #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
  112. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  113. /*
  114. * U-Boot Environment placing definitions.
  115. */
  116. #define CONFIG_ENV_SECT_SIZE 0x00010000
  117. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
  118. CONFIG_SYS_MONITOR_LEN)
  119. #define CONFIG_ENV_SIZE 0x02000
  120. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
  121. CONFIG_ENV_SECT_SIZE)
  122. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  123. /* Miscellaneous configurable options */
  124. #define CONFIG_ARCH_CPU_INIT
  125. #define CONFIG_DISPLAY_CPUINFO
  126. #define CONFIG_BOOT_PARAMS_ADDR 0x00000100
  127. #define CONFIG_CMDLINE_TAG
  128. #define CONFIG_OF_LIBFDT /* enable passing of devicetree */
  129. #define CONFIG_SETUP_MEMORY_TAGS
  130. #define CONFIG_MISC_INIT_R
  131. #define CONFIG_BOARD_LATE_INIT
  132. #define CONFIG_LOOPW /* enable loopw command */
  133. #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
  134. #define CONFIG_ZERO_BOOTDELAY_CHECK
  135. #define CONFIG_AUTOBOOT_KEYED
  136. #define CONFIG_AUTOBOOT_STOP_STR " "
  137. #define CONFIG_AUTOBOOT_PROMPT \
  138. "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
  139. #define CONFIG_SYS_MEMTEST_START 0x00800000
  140. #define CONFIG_SYS_MEMTEST_END 0x04000000
  141. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
  142. #define CONFIG_IDENT_STRING "-SPEAr"
  143. #define CONFIG_SYS_LONGHELP
  144. #define CONFIG_SYS_PROMPT "X600> "
  145. #define CONFIG_CMDLINE_EDITING
  146. #define CONFIG_SYS_CBSIZE 256
  147. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  148. sizeof(CONFIG_SYS_PROMPT) + 16)
  149. #define CONFIG_SYS_MAXARGS 16
  150. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  151. #define CONFIG_SYS_LOAD_ADDR 0x00800000
  152. #define CONFIG_SYS_CONSOLE_INFO_QUIET
  153. /* Use last 2 lwords in internal SRAM for bootcounter */
  154. #define CONFIG_BOOTCOUNT_LIMIT
  155. #define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8
  156. #define CONFIG_HOSTNAME x600
  157. #define CONFIG_UBI_PART ubi0
  158. #define CONFIG_UBIFS_VOLUME rootfs
  159. #define xstr(s) str(s)
  160. #define str(s) #s
  161. #define MTDIDS_DEFAULT "nand0=nand"
  162. #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)"
  163. #define CONFIG_EXTRA_ENV_SETTINGS \
  164. "u-boot_addr=1000000\0" \
  165. "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \
  166. "load=tftp ${u-boot_addr} ${u-boot}\0" \
  167. "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\
  168. "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
  169. "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \
  170. " ${filesize};" \
  171. "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \
  172. " +${filesize}\0" \
  173. "upd=run load update\0" \
  174. "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \
  175. "part=" xstr(CONFIG_UBI_PART) "\0" \
  176. "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \
  177. "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
  178. "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
  179. " ${filesize}\0" \
  180. "upd_ubifs=run load_ubifs update_ubifs\0" \
  181. "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
  182. "ubi create ${vol} 4000000\0" \
  183. "netdev=eth0\0" \
  184. "rootpath=/opt/eldk-4.2/arm\0" \
  185. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  186. "nfsroot=${serverip}:${rootpath}\0" \
  187. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  188. "boot_part=0\0" \
  189. "altbootcmd=if test $boot_part -eq 0;then " \
  190. "echo Switching to partition 1!;" \
  191. "setenv boot_part 1;" \
  192. "else; " \
  193. "echo Switching to partition 0!;" \
  194. "setenv boot_part 0;" \
  195. "fi;" \
  196. "saveenv;boot\0" \
  197. "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
  198. "root=ubi0:rootfs rootfstype=ubifs\0" \
  199. "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
  200. "kernel_fs=/boot/uImage \0" \
  201. "kernel_addr=1000000\0" \
  202. "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \
  203. "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \
  204. "dtb_addr=1800000\0" \
  205. "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
  206. "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
  207. "addip=setenv bootargs ${bootargs} " \
  208. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  209. ":${hostname}:${netdev}:off panic=1\0" \
  210. "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
  211. "${baudrate}\0" \
  212. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  213. "net_nfs=run load_dtb load_kernel; " \
  214. "run nfsargs addip addcon addmtd addmisc;" \
  215. "bootm ${kernel_addr} - ${dtb_addr}\0" \
  216. "mtdids=" MTDIDS_DEFAULT "\0" \
  217. "mtdparts=" MTDPARTS_DEFAULT "\0" \
  218. "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
  219. " addcon addmisc addmtd;" \
  220. "bootm ${kernel_addr} - ${dtb_addr}\0" \
  221. "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
  222. "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
  223. "ubifsload ${dtb_addr} ${dtb_fs};\0" \
  224. "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
  225. "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
  226. "bootcmd=run nand_ubifs\0" \
  227. "\0"
  228. /* Stack sizes */
  229. #define CONFIG_STACKSIZE (512 * 1024)
  230. /* Physical Memory Map */
  231. #define CONFIG_NR_DRAM_BANKS 1
  232. #define PHYS_SDRAM_1 0x00000000
  233. #define PHYS_SDRAM_1_MAXSIZE 0x40000000
  234. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  235. #define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
  236. #define CONFIG_SYS_INIT_RAM_SIZE 0x2000
  237. #define CONFIG_SYS_INIT_SP_OFFSET \
  238. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  239. #define CONFIG_SYS_INIT_SP_ADDR \
  240. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  241. /*
  242. * SPL related defines
  243. */
  244. #define CONFIG_SPL 1
  245. #define CONFIG_SPL_TEXT_BASE 0xd2800b00
  246. #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
  247. #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
  248. #define CONFIG_SPL_SERIAL_SUPPORT
  249. #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
  250. #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
  251. #define CONFIG_SPL_NO_PRINTF
  252. /*
  253. * Please select/define only one of the following
  254. * Each definition corresponds to a supported DDR chip.
  255. * DDR configuration is based on the following selection
  256. */
  257. #define CONFIG_DDR_MT47H64M16 1
  258. #define CONFIG_DDR_MT47H32M16 0
  259. #define CONFIG_DDR_MT47H128M8 0
  260. /*
  261. * Synchronous/Asynchronous operation of DDR
  262. *
  263. * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
  264. * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
  265. * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
  266. */
  267. #define CONFIG_DDR_2HCLK 1
  268. #define CONFIG_DDR_HCLK 0
  269. #define CONFIG_DDR_PLL2 0
  270. /*
  271. * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
  272. * or not. Modify/Add to only these macros to define new boot types
  273. */
  274. #define USB_BOOT_SUPPORTED 0
  275. #define PCIE_BOOT_SUPPORTED 0
  276. #define SNOR_BOOT_SUPPORTED 1
  277. #define NAND_BOOT_SUPPORTED 1
  278. #define PNOR_BOOT_SUPPORTED 0
  279. #define TFTP_BOOT_SUPPORTED 0
  280. #define UART_BOOT_SUPPORTED 0
  281. #define SPI_BOOT_SUPPORTED 0
  282. #define I2C_BOOT_SUPPORTED 0
  283. #define MMC_BOOT_SUPPORTED 0
  284. #endif /* __CONFIG_H */