tao3530.h 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366
  1. /*
  2. * Configuration settings for the TechNexion TAO-3530 SOM
  3. * equipped on Thunder baseboard.
  4. *
  5. * Edward Lin <linuxfae@technexion.com>
  6. * Tapani Utriainen <linuxfae@technexion.com>
  7. *
  8. * Copyright (C) 2013 Stefan Roese <sr@denx.de>
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. /*
  15. * High Level Configuration Options
  16. */
  17. #define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
  18. #define CONFIG_OMAP /* in a TI OMAP core */
  19. #define CONFIG_OMAP34XX /* which is a 34XX */
  20. #define CONFIG_OMAP_GPIO
  21. #define CONFIG_OMAP_COMMON
  22. #define CONFIG_SYS_GENERIC_BOARD
  23. #define MACH_TYPE_OMAP3_TAO3530 2836
  24. #define CONFIG_SDRC /* Has an SDRC controller */
  25. #include <asm/arch/cpu.h> /* get chip and board defs */
  26. #include <asm/arch/omap3.h>
  27. /*
  28. * Display CPU and Board information
  29. */
  30. #define CONFIG_DISPLAY_CPUINFO
  31. #define CONFIG_DISPLAY_BOARDINFO
  32. /* Clock Defines */
  33. #define V_OSCK 26000000 /* Clock output from T2 */
  34. #define V_SCLK (V_OSCK >> 1)
  35. #define CONFIG_MISC_INIT_R
  36. #define CONFIG_OF_LIBFDT
  37. #define CONFIG_CMDLINE_TAG
  38. #define CONFIG_SETUP_MEMORY_TAGS
  39. #define CONFIG_INITRD_TAG
  40. #define CONFIG_REVISION_TAG
  41. /*
  42. * Size of malloc() pool
  43. */
  44. #define CONFIG_SYS_MALLOC_LEN (4 << 20)
  45. #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
  46. /*
  47. * Hardware drivers
  48. */
  49. /*
  50. * NS16550 Configuration
  51. */
  52. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  53. #define CONFIG_SYS_NS16550
  54. #define CONFIG_SYS_NS16550_SERIAL
  55. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  56. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  57. /*
  58. * select serial console configuration
  59. */
  60. #define CONFIG_CONS_INDEX 3
  61. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  62. /* allow to overwrite serial and ethaddr */
  63. #define CONFIG_ENV_OVERWRITE
  64. #define CONFIG_BAUDRATE 115200
  65. #define CONFIG_GENERIC_MMC
  66. #define CONFIG_MMC
  67. #define CONFIG_OMAP_HSMMC
  68. #define CONFIG_DOS_PARTITION
  69. /* GPIO banks */
  70. #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
  71. #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */
  72. #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */
  73. #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
  74. #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
  75. /* commands to include */
  76. #include <config_cmd_default.h>
  77. #define CONFIG_CMD_CACHE
  78. #define CONFIG_CMD_EXT2 /* EXT2 Support */
  79. #define CONFIG_CMD_FAT /* FAT support */
  80. #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
  81. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  82. #define MTDIDS_DEFAULT "nand0=nand"
  83. #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
  84. "1920k(u-boot),128k(u-boot-env),"\
  85. "4m(kernel),-(fs)"
  86. #define CONFIG_CMD_I2C /* I2C serial bus support */
  87. #define CONFIG_CMD_MMC /* MMC support */
  88. #define CONFIG_CMD_NAND /* NAND support */
  89. #define CONFIG_CMD_DHCP
  90. #define CONFIG_CMD_PING
  91. #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
  92. #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
  93. #undef CONFIG_CMD_IMI /* iminfo */
  94. #undef CONFIG_CMD_IMLS /* List all found images */
  95. #define CONFIG_SYS_NO_FLASH
  96. #define CONFIG_SYS_I2C
  97. #define CONFIG_SYS_I2C_OMAP34XX
  98. #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
  99. #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
  100. #define CONFIG_I2C_MULTI_BUS
  101. /*
  102. * TWL4030
  103. */
  104. #define CONFIG_TWL4030_POWER
  105. #define CONFIG_TWL4030_LED
  106. /*
  107. * Board NAND Info.
  108. */
  109. #define CONFIG_SYS_NAND_QUIET_TEST
  110. #define CONFIG_NAND_OMAP_GPMC
  111. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  112. /* to access nand */
  113. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  114. /* to access nand at */
  115. /* CS0 */
  116. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  117. /* devices */
  118. #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
  119. /* Environment information */
  120. #define CONFIG_BOOTDELAY 3
  121. #define CONFIG_EXTRA_ENV_SETTINGS \
  122. "loadaddr=0x82000000\0" \
  123. "console=ttyO2,115200n8\0" \
  124. "mpurate=600\0" \
  125. "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
  126. "tv_mode=omapfb.mode=tv:ntsc\0" \
  127. "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
  128. "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
  129. "extra_options= \0" \
  130. "mmcdev=0\0" \
  131. "mmcroot=/dev/mmcblk0p2 rw\0" \
  132. "mmcrootfstype=ext3 rootwait\0" \
  133. "nandroot=ubi0:rootfs ubi.mtd=4\0" \
  134. "nandrootfstype=ubifs\0" \
  135. "mmcargs=setenv bootargs console=${console} " \
  136. "mpurate=${mpurate} " \
  137. "${video_mode} " \
  138. "root=${mmcroot} " \
  139. "rootfstype=${mmcrootfstype} " \
  140. "${extra_options}\0" \
  141. "nandargs=setenv bootargs console=${console} " \
  142. "mpurate=${mpurate} " \
  143. "${video_mode} " \
  144. "${network_setting} " \
  145. "root=${nandroot} " \
  146. "rootfstype=${nandrootfstype} "\
  147. "${extra_options}\0" \
  148. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  149. "bootscript=echo Running bootscript from mmc ...; " \
  150. "source ${loadaddr}\0" \
  151. "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  152. "mmcboot=echo Booting from mmc ...; " \
  153. "run mmcargs; " \
  154. "bootm ${loadaddr}\0" \
  155. "nandboot=echo Booting from nand ...; " \
  156. "run nandargs; " \
  157. "nand read ${loadaddr} 280000 400000; " \
  158. "bootm ${loadaddr}\0" \
  159. #define CONFIG_BOOTCOMMAND \
  160. "if mmc rescan ${mmcdev}; then " \
  161. "if run loadbootscript; then " \
  162. "run bootscript; " \
  163. "else " \
  164. "if run loaduimage; then " \
  165. "run mmcboot; " \
  166. "else run nandboot; " \
  167. "fi; " \
  168. "fi; " \
  169. "else run nandboot; fi"
  170. /*
  171. * Miscellaneous configurable options
  172. */
  173. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  174. #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  175. #define CONFIG_SYS_PROMPT "TAO-3530 # "
  176. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  177. /* turn on command-line edit/hist/auto */
  178. #define CONFIG_CMDLINE_EDITING
  179. #define CONFIG_COMMAND_HISTORY
  180. #define CONFIG_AUTO_COMPLETE
  181. /* Print Buffer Size */
  182. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  183. sizeof(CONFIG_SYS_PROMPT) + 16)
  184. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  185. /* Boot Argument Buffer Size */
  186. #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  187. #define CONFIG_SYS_ALT_MEMTEST 1
  188. #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
  189. /* defaults */
  190. #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
  191. #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
  192. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
  193. /* load address */
  194. #define CONFIG_SYS_TEXT_BASE 0x80008000
  195. /*
  196. * OMAP3 has 12 GP timers, they can be driven by the system clock
  197. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  198. * This rate is divided by a local divisor.
  199. */
  200. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  201. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  202. /*
  203. * Stack sizes
  204. *
  205. * The stack sizes are set up in start.S using the settings below
  206. */
  207. #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
  208. /*
  209. * Physical Memory Map
  210. */
  211. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  212. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  213. #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
  214. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  215. /*
  216. * FLASH and environment organization
  217. */
  218. /* **** PISMO SUPPORT *** */
  219. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  220. #define CONFIG_SYS_FLASH_BASE NAND_BASE
  221. /* Monitor at start of flash */
  222. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  223. #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
  224. #define CONFIG_ENV_IS_IN_NAND 1
  225. #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
  226. #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
  227. #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
  228. #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
  229. #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
  230. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  231. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  232. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  233. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  234. CONFIG_SYS_INIT_RAM_SIZE - \
  235. GENERATED_GBL_DATA_SIZE)
  236. #define CONFIG_OMAP3_SPI
  237. /*
  238. * USB
  239. *
  240. * Currently only EHCI is enabled, the MUSB OTG controller
  241. * is not enabled.
  242. */
  243. /* USB EHCI */
  244. #define CONFIG_CMD_USB
  245. #define CONFIG_USB_EHCI
  246. #define CONFIG_USB_EHCI_OMAP
  247. #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
  248. #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
  249. #define CONFIG_USB_HOST_ETHER
  250. #define CONFIG_USB_ETHER_SMSC95XX
  251. #define CONFIG_USB_ETHER
  252. #define CONFIG_USB_ETHER_RNDIS
  253. #define CONFIG_USB_STORAGE
  254. #define CONGIG_CMD_STORAGE
  255. /* Defines for SPL */
  256. #define CONFIG_SPL 1
  257. #define CONFIG_SPL_FRAMEWORK
  258. #define CONFIG_SPL_NAND_SIMPLE
  259. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
  260. #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
  261. #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
  262. #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
  263. #define CONFIG_SPL_BOARD_INIT
  264. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  265. #define CONFIG_SPL_LIBDISK_SUPPORT
  266. #define CONFIG_SPL_I2C_SUPPORT
  267. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  268. #define CONFIG_SPL_MMC_SUPPORT
  269. #define CONFIG_SPL_FAT_SUPPORT
  270. #define CONFIG_SPL_SERIAL_SUPPORT
  271. #define CONFIG_SPL_NAND_SUPPORT
  272. #define CONFIG_SPL_NAND_BASE
  273. #define CONFIG_SPL_NAND_DRIVERS
  274. #define CONFIG_SPL_NAND_ECC
  275. #define CONFIG_SPL_GPIO_SUPPORT
  276. #define CONFIG_SPL_POWER_SUPPORT
  277. #define CONFIG_SPL_OMAP3_ID_NAND
  278. #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
  279. /* NAND boot config */
  280. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  281. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  282. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  283. #define CONFIG_SYS_NAND_OOBSIZE 64
  284. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  285. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  286. /*
  287. * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
  288. * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
  289. */
  290. #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
  291. 10, 11, 12, 13 }
  292. #define CONFIG_SYS_NAND_ECCSIZE 512
  293. #define CONFIG_SYS_NAND_ECCBYTES 3
  294. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
  295. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  296. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  297. #define CONFIG_SPL_TEXT_BASE 0x40200800
  298. #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
  299. #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
  300. /*
  301. * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
  302. * older x-loader implementations. And move the BSS area so that it
  303. * doesn't overlap with TEXT_BASE.
  304. */
  305. #define CONFIG_SYS_TEXT_BASE 0x80008000
  306. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  307. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
  308. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  309. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  310. #endif /* __CONFIG_H */