socfpga_cyclone5.h 6.6 KB

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  1. /*
  2. * Copyright (C) 2012 Altera Corporation <www.altera.com>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #include <asm/arch/socfpga_base_addrs.h>
  9. #include "../../board/altera/socfpga/pinmux_config.h"
  10. #include "../../board/altera/socfpga/iocsr_config.h"
  11. #include "../../board/altera/socfpga/pll_config.h"
  12. /*
  13. * High level configuration
  14. */
  15. /* Virtual target or real hardware */
  16. #define CONFIG_SOCFPGA_VIRTUAL_TARGET
  17. #define CONFIG_ARMV7
  18. #define CONFIG_SYS_DCACHE_OFF
  19. #undef CONFIG_USE_IRQ
  20. #define CONFIG_MISC_INIT_R
  21. #define CONFIG_SINGLE_BOOTLOADER
  22. #define CONFIG_SOCFPGA
  23. /* base address for .text section */
  24. #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  25. #define CONFIG_SYS_TEXT_BASE 0x08000040
  26. #else
  27. #define CONFIG_SYS_TEXT_BASE 0x01000040
  28. #endif
  29. #define CONFIG_SYS_LOAD_ADDR 0x7fc0
  30. /* Console I/O Buffer Size */
  31. #define CONFIG_SYS_CBSIZE 256
  32. /* Monitor Command Prompt */
  33. #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
  34. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  35. sizeof(CONFIG_SYS_PROMPT) + 16)
  36. /*
  37. * Display CPU and Board Info
  38. */
  39. #define CONFIG_DISPLAY_CPUINFO
  40. #define CONFIG_DISPLAY_BOARDINFO
  41. /*
  42. * Enable early stage initialization at C environment
  43. */
  44. #define CONFIG_BOARD_EARLY_INIT_F
  45. /* flat device tree */
  46. #define CONFIG_OF_LIBFDT
  47. /* skip updating the FDT blob */
  48. #define CONFIG_FDT_BLOB_SKIP_UPDATE
  49. /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
  50. #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
  51. #define CONFIG_SPL_RAM_DEVICE
  52. #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
  53. #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
  54. #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
  55. /*
  56. * Memory allocation (MALLOC)
  57. */
  58. /* Room required on the stack for the environment data */
  59. #define CONFIG_ENV_SIZE 1024
  60. /* Size of DRAM reserved for malloc() use */
  61. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
  62. /* SP location before relocation, must use scratch RAM */
  63. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
  64. /* Reserving 0x100 space at back of scratch RAM for debug info */
  65. #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
  66. /* Stack pointer prior relocation, must situated at on-chip RAM */
  67. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  68. CONFIG_SYS_INIT_RAM_SIZE - \
  69. GENERATED_GBL_DATA_SIZE)
  70. /*
  71. * Command line configuration.
  72. */
  73. #define CONFIG_SYS_NO_FLASH
  74. #include <config_cmd_default.h>
  75. /* FAT file system support */
  76. #define CONFIG_CMD_FAT
  77. /*
  78. * Misc
  79. */
  80. #define CONFIG_DOS_PARTITION 1
  81. #ifdef CONFIG_SPL_BUILD
  82. #undef CONFIG_PARTITIONS
  83. #endif
  84. /*
  85. * Environment setup
  86. */
  87. /* Delay before automatically booting the default image */
  88. #define CONFIG_BOOTDELAY 3
  89. /* Enable auto completion of commands using TAB */
  90. #define CONFIG_AUTO_COMPLETE
  91. /* use "hush" command parser */
  92. #define CONFIG_SYS_HUSH_PARSER
  93. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  94. #define CONFIG_CMD_RUN
  95. #define CONFIG_BOOTCOMMAND "run ramboot"
  96. /*
  97. * arguments passed to the bootm command. The value of
  98. * CONFIG_BOOTARGS goes into the environment value "bootargs".
  99. * Do note the value will overide also the chosen node in FDT blob.
  100. */
  101. #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
  102. #define CONFIG_EXTRA_ENV_SETTINGS \
  103. "verify=n\0" \
  104. "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  105. "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
  106. "bootm ${loadaddr} - ${fdt_addr}\0" \
  107. "bootimage=uImage\0" \
  108. "fdt_addr=100\0" \
  109. "fsloadcmd=ext2load\0" \
  110. "bootm ${loadaddr} - ${fdt_addr}\0" \
  111. "qspiroot=/dev/mtdblock0\0" \
  112. "qspirootfstype=jffs2\0" \
  113. "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
  114. " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
  115. "bootm ${loadaddr} - ${fdt_addr}\0"
  116. /* using environment setting for stdin, stdout, stderr */
  117. #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  118. /* Enable the call to overwrite_console() */
  119. #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
  120. /* Enable overwrite of previous console environment settings */
  121. #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
  122. /* max number of command args */
  123. #define CONFIG_SYS_MAXARGS 16
  124. /*
  125. * Hardware drivers
  126. */
  127. /*
  128. * SDRAM Memory Map
  129. */
  130. /* We have 1 bank of DRAM */
  131. #define CONFIG_NR_DRAM_BANKS 1
  132. /* SDRAM Bank #1 */
  133. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  134. /* SDRAM memory size */
  135. #define PHYS_SDRAM_1_SIZE 0x40000000
  136. #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
  137. #define CONFIG_SYS_MEMTEST_START 0x00000000
  138. #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
  139. /*
  140. * NS16550 Configuration
  141. */
  142. #define UART0_BASE SOCFPGA_UART0_ADDRESS
  143. #define CONFIG_SYS_NS16550
  144. #define CONFIG_SYS_NS16550_SERIAL
  145. #define CONFIG_SYS_NS16550_REG_SIZE -4
  146. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  147. #define CONFIG_CONS_INDEX 1
  148. #define CONFIG_SYS_NS16550_COM1 UART0_BASE
  149. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
  150. #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  151. #define V_NS16550_CLK 1000000
  152. #else
  153. #define V_NS16550_CLK 100000000
  154. #endif
  155. #define CONFIG_BAUDRATE 115200
  156. /*
  157. * FLASH
  158. */
  159. #define CONFIG_SYS_NO_FLASH
  160. /*
  161. * L4 OSC1 Timer 0
  162. */
  163. /* This timer use eosc1 where the clock frequency is fixed
  164. * throughout any condition */
  165. #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
  166. /* reload value when timer count to zero */
  167. #define TIMER_LOAD_VAL 0xFFFFFFFF
  168. /* Timer info */
  169. #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  170. #define CONFIG_SYS_TIMER_RATE 2400000
  171. #else
  172. #define CONFIG_SYS_TIMER_RATE 25000000
  173. #endif
  174. #define CONFIG_SYS_TIMER_COUNTS_DOWN
  175. #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
  176. #define CONFIG_ENV_IS_NOWHERE
  177. /*
  178. * L4 Watchdog
  179. */
  180. #define CONFIG_HW_WATCHDOG
  181. #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
  182. #define CONFIG_DESIGNWARE_WATCHDOG
  183. #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
  184. /* Clocks source frequency to watchdog timer */
  185. #define CONFIG_DW_WDT_CLOCK_KHZ 25000
  186. /*
  187. * SPL "Second Program Loader" aka Initial Software
  188. */
  189. /* Enable building of SPL globally */
  190. #define CONFIG_SPL 1
  191. #define CONFIG_SPL_FRAMEWORK
  192. /* TEXT_BASE for linking the SPL binary */
  193. #define CONFIG_SPL_TEXT_BASE 0xFFFF0000
  194. /* Stack size for SPL */
  195. #define CONFIG_SPL_STACK_SIZE (4 * 1024)
  196. /* MALLOC size for SPL */
  197. #define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
  198. #define CONFIG_SPL_SERIAL_SUPPORT
  199. #define CONFIG_SPL_BOARD_INIT
  200. #define CHUNKSZ_CRC32 (1 * 1024)
  201. #define CONFIG_CRC32_VERIFY
  202. /* Linker script for SPL */
  203. #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
  204. /* Support for common/libcommon.o in SPL binary */
  205. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  206. /* Support for lib/libgeneric.o in SPL binary */
  207. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  208. /* Support for watchdog */
  209. #define CONFIG_SPL_WATCHDOG_SUPPORT
  210. #endif /* __CONFIG_H */