palmtreo680.h 8.4 KB

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  1. /*
  2. * Palm Treo 680 configuration file
  3. *
  4. * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
  5. *
  6. * This file is released under the terms of GPL v2 and any later version.
  7. * See the file COPYING in the root directory of the source tree for details.
  8. *
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Board Configuration Options
  14. */
  15. #define CONFIG_CPU_PXA27X
  16. #define CONFIG_PALMTREO680
  17. #define CONFIG_MACH_TYPE MACH_TYPE_TREO680
  18. #define CONFIG_SYS_MALLOC_LEN (4096*1024)
  19. #define CONFIG_LZMA
  20. /*
  21. * Serial Console Configuration
  22. */
  23. #define CONFIG_PXA_SERIAL
  24. #define CONFIG_FFUART 1
  25. #define CONFIG_BAUDRATE 9600
  26. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  27. #define CONFIG_CONS_INDEX 3
  28. /* we have nand (although technically nand *is* flash...) */
  29. #define CONFIG_SYS_NO_FLASH
  30. #define CONFIG_LCD
  31. /* #define CONFIG_KEYBOARD */ /* TODO */
  32. /*
  33. * Bootloader Components Configuration
  34. */
  35. #include <config_cmd_default.h>
  36. #undef CONFIG_CMD_FPGA
  37. #undef CONFIG_CMD_LOADS
  38. #undef CONFIG_CMD_NET
  39. #undef CONFIG_CMD_NFS
  40. #undef CONFIG_CMD_IMLS
  41. #undef CONFIG_CMD_FLASH
  42. #undef CONFIG_CMD_SETGETDCR
  43. #undef CONFIG_CMD_SOURCE
  44. #undef CONFIG_CMD_XIMG
  45. #define CONFIG_CMD_ENV
  46. #define CONFIG_CMD_MMC
  47. #define CONFIG_CMD_NAND
  48. #define CONFIG_CMDLINE_TAG
  49. #define CONFIG_SETUP_MEMORY_TAGS
  50. /*
  51. * MMC Card Configuration
  52. */
  53. #ifdef CONFIG_CMD_MMC
  54. #define CONFIG_MMC
  55. #define CONFIG_GENERIC_MMC
  56. #define CONFIG_PXA_MMC_GENERIC
  57. #define CONFIG_CMD_FAT
  58. #define CONFIG_CMD_EXT2
  59. #define CONFIG_DOS_PARTITION
  60. #endif
  61. /*
  62. * LCD
  63. */
  64. #ifdef CONFIG_LCD
  65. #define CONFIG_PXA_LCD
  66. #define CONFIG_ACX544AKN
  67. #define CONFIG_LCD_LOGO
  68. #define CONFIG_SYS_LCD_PXA_NO_L_BIAS /* don't configure GPIO77 as L_BIAS */
  69. #define LCD_BPP LCD_COLOR16
  70. #define CONFIG_FB_ADDR 0x5c000000 /* internal SRAM */
  71. #define CONFIG_CMD_BMP
  72. #define CONFIG_SPLASH_SCREEN /* requires "splashimage" env var */
  73. #define CONFIG_SPLASH_SCREEN_ALIGN /* requires "splashpos" env var */
  74. #define CONFIG_VIDEO_BMP_GZIP
  75. #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
  76. #endif
  77. /*
  78. * KGDB
  79. */
  80. #ifdef CONFIG_CMD_KGDB
  81. #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
  82. #endif
  83. /*
  84. * HUSH Shell Configuration
  85. */
  86. #define CONFIG_SYS_HUSH_PARSER 1
  87. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  88. #define CONFIG_SYS_LONGHELP
  89. #ifdef CONFIG_SYS_HUSH_PARSER
  90. #define CONFIG_SYS_PROMPT "$ "
  91. #else
  92. #endif
  93. #define CONFIG_SYS_CBSIZE 256
  94. #define CONFIG_SYS_PBSIZE \
  95. (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  96. #define CONFIG_SYS_MAXARGS 16
  97. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  98. #define CONFIG_SYS_DEVICE_NULLDEV 1
  99. /*
  100. * Clock Configuration
  101. */
  102. #undef CONFIG_SYS_CLKS_IN_HZ
  103. #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
  104. /*
  105. * Stack sizes
  106. */
  107. #define CONFIG_STACKSIZE (128*1024) /* regular stack */
  108. #ifdef CONFIG_USE_IRQ
  109. #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
  110. #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
  111. #endif
  112. /*
  113. * DRAM Map
  114. */
  115. #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
  116. #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
  117. #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
  118. #define CONFIG_SYS_DRAM_BASE 0xa0000000
  119. #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
  120. #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
  121. #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
  122. #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
  123. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  124. /*
  125. * GPIO settings
  126. */
  127. #define CONFIG_SYS_GAFR0_L_VAL 0x0E000000
  128. #define CONFIG_SYS_GAFR0_U_VAL 0xA500001A
  129. #define CONFIG_SYS_GAFR1_L_VAL 0x60000002
  130. #define CONFIG_SYS_GAFR1_U_VAL 0xAAA07959
  131. #define CONFIG_SYS_GAFR2_L_VAL 0x02AAAAAA
  132. #define CONFIG_SYS_GAFR2_U_VAL 0x41440F08
  133. #define CONFIG_SYS_GAFR3_L_VAL 0x56AA95FF
  134. #define CONFIG_SYS_GAFR3_U_VAL 0x00001401
  135. #define CONFIG_SYS_GPCR0_VAL 0x1FF80400
  136. #define CONFIG_SYS_GPCR1_VAL 0x03003FC1
  137. #define CONFIG_SYS_GPCR2_VAL 0x01C1E000
  138. #define CONFIG_SYS_GPCR3_VAL 0x01C1E000
  139. #define CONFIG_SYS_GPDR0_VAL 0xCFF90400
  140. #define CONFIG_SYS_GPDR1_VAL 0xFB22BFC1
  141. #define CONFIG_SYS_GPDR2_VAL 0x93CDFFDF
  142. #define CONFIG_SYS_GPDR3_VAL 0x0069FF81
  143. #define CONFIG_SYS_GPSR0_VAL 0x02000018
  144. #define CONFIG_SYS_GPSR1_VAL 0x00000000
  145. #define CONFIG_SYS_GPSR2_VAL 0x000C0000
  146. #define CONFIG_SYS_GPSR3_VAL 0x00080000
  147. #define CONFIG_SYS_PSSR_VAL 0x30
  148. /*
  149. * Clock settings
  150. */
  151. #define CONFIG_SYS_CKEN 0x01ffffff
  152. #define CONFIG_SYS_CCCR 0x02000210
  153. /*
  154. * Memory settings
  155. */
  156. #define CONFIG_SYS_MSC0_VAL 0x7ff844c8
  157. #define CONFIG_SYS_MSC1_VAL 0x7ff86ab4
  158. #define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
  159. #define CONFIG_SYS_MDCNFG_VAL 0x0B880acd
  160. #define CONFIG_SYS_MDREFR_VAL 0x201fa031
  161. #define CONFIG_SYS_MDMRS_VAL 0x00320032
  162. #define CONFIG_SYS_FLYCNFG_VAL 0x00000000
  163. #define CONFIG_SYS_SXCNFG_VAL 0x40044004
  164. #define CONFIG_SYS_MECR_VAL 0x00000003
  165. #define CONFIG_SYS_MCMEM0_VAL 0x0001c391
  166. #define CONFIG_SYS_MCMEM1_VAL 0x0001c391
  167. #define CONFIG_SYS_MCATT0_VAL 0x0001c391
  168. #define CONFIG_SYS_MCATT1_VAL 0x0001c391
  169. #define CONFIG_SYS_MCIO0_VAL 0x00014611
  170. #define CONFIG_SYS_MCIO1_VAL 0x0001c391
  171. /*
  172. * USB
  173. */
  174. #define CONFIG_USB_DEVICE
  175. #define CONFIG_USB_TTY
  176. #define CONFIG_USB_DEV_PULLUP_GPIO 114
  177. /*
  178. * SPL
  179. */
  180. #define CONFIG_SPL 1
  181. #define CONFIG_SPL_TEXT_BASE 0xa1700000 /* IPL loads SPL here */
  182. #define CONFIG_SPL_STACK 0x5c040000 /* end of internal SRAM */
  183. #define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */
  184. #define CONFIG_SPL_NAND_DOCG4 /* use lean docg4 nand spl driver */
  185. #define CONFIG_SPL_LIBGENERIC_SUPPORT /* spl uses memcpy */
  186. /*
  187. * NAND
  188. */
  189. #define CONFIG_NAND_DOCG4
  190. #define CONFIG_SYS_NAND_SELF_INIT
  191. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */
  192. #define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */
  193. #define CONFIG_SYS_NAND_PAGE_SIZE 0x200
  194. #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
  195. #define CONFIG_BITREVERSE /* needed by docg4 driver */
  196. #define CONFIG_BCH /* needed by docg4 driver */
  197. /*
  198. * IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image. It
  199. * will be rounded up to the next 64k boundary (the spl flash block size), so it
  200. * does not have to be exact, but you must ensure that it is not less than the
  201. * actual image size, or it may fail to boot (bricked phone)!
  202. * (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.)
  203. */
  204. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */
  205. /*
  206. * This is the byte offset into the flash at which the concatenated spl + u-boot
  207. * image is placed. It must be at the start of a block (256k boundary). Blocks
  208. * 0 - 5 are write-protected, so we start at block 6.
  209. */
  210. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000 /* block 6 */
  211. /* DRAM address to which u-boot proper is loaded (before it relocates itself) */
  212. #define CONFIG_SYS_NAND_U_BOOT_DST 0xa0000000
  213. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  214. /* passed to linker by Makefile as arg to -Ttext option */
  215. #define CONFIG_SYS_TEXT_BASE 0xa0000000
  216. #define CONFIG_SYS_INIT_SP_ADDR 0x5c040000 /* end of internal SRAM */
  217. /*
  218. * environment
  219. */
  220. #define CONFIG_ENV_IS_NOWHERE
  221. #define CONFIG_BUILD_ENVCRC
  222. #define CONFIG_ENV_SIZE 0x200
  223. #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  224. #define CONFIG_EXTRA_ENV_SETTINGS \
  225. "stdin=usbtty\0" \
  226. "stdout=usbtty\0" \
  227. "stderr=usbtty"
  228. #define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \
  229. ip=192.168.11.102:::255.255.255.0:treo:usb0"
  230. #define CONFIG_BOOTDELAY 3
  231. #if 0 /* example: try 2nd mmc partition, then nand */
  232. #define CONFIG_BOOTCOMMAND \
  233. "mmc rescan; " \
  234. "if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then " \
  235. "bootm 0xa1000000; " \
  236. "elif nand read 0xa1000000 0x280000 0x240000; then " \
  237. "bootm 0xa1000000; " \
  238. "fi; "
  239. #endif
  240. /* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */
  241. #define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000
  242. #define CONFIG_SYS_DCACHE_OFF
  243. #define CONFIG_SYS_ICACHE_OFF
  244. #endif /* __CONFIG_H */