p1_p2_rdb_pc.h 32 KB

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  1. /*
  2. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /*
  7. * QorIQ RDB boards configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #define CONFIG_SYS_GENERIC_BOARD
  12. #define CONFIG_DISPLAY_BOARDINFO
  13. #ifdef CONFIG_36BIT
  14. #define CONFIG_PHYS_64BIT
  15. #endif
  16. #if defined(CONFIG_P1020MBG)
  17. #define CONFIG_BOARDNAME "P1020MBG-PC"
  18. #define CONFIG_P1020
  19. #define CONFIG_VSC7385_ENET
  20. #define CONFIG_SLIC
  21. #define __SW_BOOT_MASK 0x03
  22. #define __SW_BOOT_NOR 0xe4
  23. #define __SW_BOOT_SD 0x54
  24. #define CONFIG_SYS_L2_SIZE (256 << 10)
  25. #endif
  26. #if defined(CONFIG_P1020UTM)
  27. #define CONFIG_BOARDNAME "P1020UTM-PC"
  28. #define CONFIG_P1020
  29. #define __SW_BOOT_MASK 0x03
  30. #define __SW_BOOT_NOR 0xe0
  31. #define __SW_BOOT_SD 0x50
  32. #define CONFIG_SYS_L2_SIZE (256 << 10)
  33. #endif
  34. #if defined(CONFIG_P1020RDB_PC)
  35. #define CONFIG_BOARDNAME "P1020RDB-PC"
  36. #define CONFIG_NAND_FSL_ELBC
  37. #define CONFIG_P1020
  38. #define CONFIG_SPI_FLASH
  39. #define CONFIG_VSC7385_ENET
  40. #define CONFIG_SLIC
  41. #define __SW_BOOT_MASK 0x03
  42. #define __SW_BOOT_NOR 0x5c
  43. #define __SW_BOOT_SPI 0x1c
  44. #define __SW_BOOT_SD 0x9c
  45. #define __SW_BOOT_NAND 0xec
  46. #define __SW_BOOT_PCIE 0x6c
  47. #define CONFIG_SYS_L2_SIZE (256 << 10)
  48. #endif
  49. /*
  50. * P1020RDB-PD board has user selectable switches for evaluating different
  51. * frequency and boot options for the P1020 device. The table that
  52. * follow describe the available options. The front six binary number was in
  53. * accordance with SW3[1:6].
  54. * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
  55. * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
  56. * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
  57. * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
  58. * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
  59. * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
  60. * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  61. */
  62. #if defined(CONFIG_P1020RDB_PD)
  63. #define CONFIG_BOARDNAME "P1020RDB-PD"
  64. #define CONFIG_NAND_FSL_ELBC
  65. #define CONFIG_P1020
  66. #define CONFIG_SPI_FLASH
  67. #define CONFIG_VSC7385_ENET
  68. #define CONFIG_SLIC
  69. #define __SW_BOOT_MASK 0x03
  70. #define __SW_BOOT_NOR 0x64
  71. #define __SW_BOOT_SPI 0x34
  72. #define __SW_BOOT_SD 0x24
  73. #define __SW_BOOT_NAND 0x44
  74. #define __SW_BOOT_PCIE 0x74
  75. #define CONFIG_SYS_L2_SIZE (256 << 10)
  76. #endif
  77. #if defined(CONFIG_P1021RDB)
  78. #define CONFIG_BOARDNAME "P1021RDB-PC"
  79. #define CONFIG_NAND_FSL_ELBC
  80. #define CONFIG_P1021
  81. #define CONFIG_QE
  82. #define CONFIG_SPI_FLASH
  83. #define CONFIG_VSC7385_ENET
  84. #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
  85. addresses in the LBC */
  86. #define __SW_BOOT_MASK 0x03
  87. #define __SW_BOOT_NOR 0x5c
  88. #define __SW_BOOT_SPI 0x1c
  89. #define __SW_BOOT_SD 0x9c
  90. #define __SW_BOOT_NAND 0xec
  91. #define __SW_BOOT_PCIE 0x6c
  92. #define CONFIG_SYS_L2_SIZE (256 << 10)
  93. #endif
  94. #if defined(CONFIG_P1024RDB)
  95. #define CONFIG_BOARDNAME "P1024RDB"
  96. #define CONFIG_NAND_FSL_ELBC
  97. #define CONFIG_P1024
  98. #define CONFIG_SLIC
  99. #define CONFIG_SPI_FLASH
  100. #define __SW_BOOT_MASK 0xf3
  101. #define __SW_BOOT_NOR 0x00
  102. #define __SW_BOOT_SPI 0x08
  103. #define __SW_BOOT_SD 0x04
  104. #define __SW_BOOT_NAND 0x0c
  105. #define CONFIG_SYS_L2_SIZE (256 << 10)
  106. #endif
  107. #if defined(CONFIG_P1025RDB)
  108. #define CONFIG_BOARDNAME "P1025RDB"
  109. #define CONFIG_NAND_FSL_ELBC
  110. #define CONFIG_P1025
  111. #define CONFIG_QE
  112. #define CONFIG_SLIC
  113. #define CONFIG_SPI_FLASH
  114. #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
  115. addresses in the LBC */
  116. #define __SW_BOOT_MASK 0xf3
  117. #define __SW_BOOT_NOR 0x00
  118. #define __SW_BOOT_SPI 0x08
  119. #define __SW_BOOT_SD 0x04
  120. #define __SW_BOOT_NAND 0x0c
  121. #define CONFIG_SYS_L2_SIZE (256 << 10)
  122. #endif
  123. #if defined(CONFIG_P2020RDB)
  124. #define CONFIG_BOARDNAME "P2020RDB-PCA"
  125. #define CONFIG_NAND_FSL_ELBC
  126. #define CONFIG_P2020
  127. #define CONFIG_SPI_FLASH
  128. #define CONFIG_VSC7385_ENET
  129. #define __SW_BOOT_MASK 0x03
  130. #define __SW_BOOT_NOR 0xc8
  131. #define __SW_BOOT_SPI 0x28
  132. #define __SW_BOOT_SD 0x68 /* or 0x18 */
  133. #define __SW_BOOT_NAND 0xe8
  134. #define __SW_BOOT_PCIE 0xa8
  135. #define CONFIG_SYS_L2_SIZE (512 << 10)
  136. #endif
  137. #ifdef CONFIG_SDCARD
  138. #define CONFIG_SPL 1
  139. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  140. #define CONFIG_SPL_ENV_SUPPORT
  141. #define CONFIG_SPL_SERIAL_SUPPORT
  142. #define CONFIG_SPL_MMC_SUPPORT
  143. #define CONFIG_SPL_MMC_MINIMAL
  144. #define CONFIG_SPL_FLUSH_IMAGE
  145. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  146. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  147. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  148. #define CONFIG_SPL_I2C_SUPPORT
  149. #define CONFIG_FSL_LAW /* Use common FSL init code */
  150. #define CONFIG_SYS_TEXT_BASE 0x11001000
  151. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  152. #define CONFIG_SPL_PAD_TO 0x20000
  153. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  154. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  155. #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
  156. #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
  157. #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
  158. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  159. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  160. #define CONFIG_SPL_MMC_BOOT
  161. #ifdef CONFIG_SPL_BUILD
  162. #define CONFIG_SPL_COMMON_INIT_DDR
  163. #endif
  164. #endif
  165. #ifdef CONFIG_SPIFLASH
  166. #define CONFIG_SPL 1
  167. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  168. #define CONFIG_SPL_ENV_SUPPORT
  169. #define CONFIG_SPL_SERIAL_SUPPORT
  170. #define CONFIG_SPL_SPI_SUPPORT
  171. #define CONFIG_SPL_SPI_FLASH_SUPPORT
  172. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  173. #define CONFIG_SPL_FLUSH_IMAGE
  174. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  175. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  176. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  177. #define CONFIG_SPL_I2C_SUPPORT
  178. #define CONFIG_FSL_LAW /* Use common FSL init code */
  179. #define CONFIG_SYS_TEXT_BASE 0x11001000
  180. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  181. #define CONFIG_SPL_PAD_TO 0x20000
  182. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  183. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  184. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
  185. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
  186. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
  187. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  188. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  189. #define CONFIG_SPL_SPI_BOOT
  190. #ifdef CONFIG_SPL_BUILD
  191. #define CONFIG_SPL_COMMON_INIT_DDR
  192. #endif
  193. #endif
  194. #ifdef CONFIG_NAND
  195. #define CONFIG_SPL 1
  196. #define CONFIG_TPL 1
  197. #ifdef CONFIG_TPL_BUILD
  198. #define CONFIG_SPL_NAND_BOOT
  199. #define CONFIG_SPL_FLUSH_IMAGE
  200. #define CONFIG_SPL_ENV_SUPPORT
  201. #define CONFIG_SPL_NAND_INIT
  202. #define CONFIG_SPL_SERIAL_SUPPORT
  203. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  204. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  205. #define CONFIG_SPL_I2C_SUPPORT
  206. #define CONFIG_SPL_NAND_SUPPORT
  207. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  208. #define CONFIG_SPL_COMMON_INIT_DDR
  209. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  210. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  211. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  212. #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
  213. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  214. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  215. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  216. #elif defined(CONFIG_SPL_BUILD)
  217. #define CONFIG_SPL_INIT_MINIMAL
  218. #define CONFIG_SPL_SERIAL_SUPPORT
  219. #define CONFIG_SPL_NAND_SUPPORT
  220. #define CONFIG_SPL_FLUSH_IMAGE
  221. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  222. #define CONFIG_SPL_TEXT_BASE 0xff800000
  223. #define CONFIG_SPL_MAX_SIZE 4096
  224. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  225. #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
  226. #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
  227. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  228. #endif /* not CONFIG_TPL_BUILD */
  229. #define CONFIG_SPL_PAD_TO 0x20000
  230. #define CONFIG_TPL_PAD_TO 0x20000
  231. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  232. #define CONFIG_SYS_TEXT_BASE 0x11001000
  233. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  234. #endif
  235. #ifndef CONFIG_SYS_TEXT_BASE
  236. #define CONFIG_SYS_TEXT_BASE 0xeff40000
  237. #endif
  238. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  239. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  240. #endif
  241. #ifndef CONFIG_SYS_MONITOR_BASE
  242. #ifdef CONFIG_SPL_BUILD
  243. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  244. #else
  245. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  246. #endif
  247. #endif
  248. /* High Level Configuration Options */
  249. #define CONFIG_BOOKE
  250. #define CONFIG_E500
  251. #define CONFIG_MP
  252. #define CONFIG_FSL_ELBC
  253. #define CONFIG_PCI
  254. #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
  255. #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
  256. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  257. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  258. #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  259. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  260. #define CONFIG_FSL_LAW
  261. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  262. #define CONFIG_ENV_OVERWRITE
  263. #define CONFIG_CMD_SATA
  264. #define CONFIG_SATA_SIL
  265. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  266. #define CONFIG_LIBATA
  267. #define CONFIG_LBA48
  268. #if defined(CONFIG_P2020RDB)
  269. #define CONFIG_SYS_CLK_FREQ 100000000
  270. #else
  271. #define CONFIG_SYS_CLK_FREQ 66666666
  272. #endif
  273. #define CONFIG_DDR_CLK_FREQ 66666666
  274. #define CONFIG_HWCONFIG
  275. /*
  276. * These can be toggled for performance analysis, otherwise use default.
  277. */
  278. #define CONFIG_L2_CACHE
  279. #define CONFIG_BTB
  280. #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
  281. #define CONFIG_ENABLE_36BIT_PHYS
  282. #ifdef CONFIG_PHYS_64BIT
  283. #define CONFIG_ADDR_MAP 1
  284. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  285. #endif
  286. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  287. #define CONFIG_SYS_MEMTEST_END 0x1fffffff
  288. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  289. #define CONFIG_SYS_CCSRBAR 0xffe00000
  290. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  291. /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
  292. SPL code*/
  293. #ifdef CONFIG_SPL_BUILD
  294. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  295. #endif
  296. /* DDR Setup */
  297. #define CONFIG_SYS_FSL_DDR3
  298. #define CONFIG_SYS_DDR_RAW_TIMING
  299. #define CONFIG_DDR_SPD
  300. #define CONFIG_SYS_SPD_BUS_NUM 1
  301. #define SPD_EEPROM_ADDRESS 0x52
  302. #undef CONFIG_FSL_DDR_INTERACTIVE
  303. #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
  304. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
  305. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  306. #else
  307. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
  308. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  309. #endif
  310. #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  311. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  312. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  313. #define CONFIG_NUM_DDR_CONTROLLERS 1
  314. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  315. /* Default settings for DDR3 */
  316. #ifndef CONFIG_P2020RDB
  317. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  318. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  319. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  320. #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
  321. #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
  322. #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
  323. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  324. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  325. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  326. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  327. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  328. #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
  329. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  330. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  331. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  332. #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
  333. #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
  334. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  335. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  336. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  337. #define CONFIG_SYS_DDR_TIMING_0 0x00330004
  338. #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
  339. #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
  340. #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
  341. #define CONFIG_SYS_DDR_MODE_1 0x40461520
  342. #define CONFIG_SYS_DDR_MODE_2 0x8000c000
  343. #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
  344. #endif
  345. #undef CONFIG_CLOCKS_IN_MHZ
  346. /*
  347. * Memory map
  348. *
  349. * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
  350. * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
  351. * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
  352. * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
  353. * (early boot only)
  354. * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
  355. * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
  356. * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
  357. * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
  358. * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  359. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
  360. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  361. */
  362. /*
  363. * Local Bus Definitions
  364. */
  365. #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
  366. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
  367. #define CONFIG_SYS_FLASH_BASE 0xec000000
  368. #elif defined(CONFIG_P1020UTM)
  369. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
  370. #define CONFIG_SYS_FLASH_BASE 0xee000000
  371. #else
  372. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
  373. #define CONFIG_SYS_FLASH_BASE 0xef000000
  374. #endif
  375. #ifdef CONFIG_PHYS_64BIT
  376. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  377. #else
  378. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  379. #endif
  380. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  381. | BR_PS_16 | BR_V)
  382. #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
  383. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  384. #define CONFIG_SYS_FLASH_QUIET_TEST
  385. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  386. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  387. #undef CONFIG_SYS_FLASH_CHECKSUM
  388. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  389. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  390. #define CONFIG_FLASH_CFI_DRIVER
  391. #define CONFIG_SYS_FLASH_CFI
  392. #define CONFIG_SYS_FLASH_EMPTY_INFO
  393. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  394. /* Nand Flash */
  395. #ifdef CONFIG_NAND_FSL_ELBC
  396. #define CONFIG_SYS_NAND_BASE 0xff800000
  397. #ifdef CONFIG_PHYS_64BIT
  398. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  399. #else
  400. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  401. #endif
  402. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  403. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  404. #define CONFIG_MTD_NAND_VERIFY_WRITE
  405. #define CONFIG_CMD_NAND
  406. #if defined(CONFIG_P1020RDB_PD)
  407. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  408. #else
  409. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
  410. #endif
  411. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  412. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  413. | BR_PS_8 /* Port Size = 8 bit */ \
  414. | BR_MS_FCM /* MSEL = FCM */ \
  415. | BR_V) /* valid */
  416. #if defined(CONFIG_P1020RDB_PD)
  417. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
  418. | OR_FCM_PGS /* Large Page*/ \
  419. | OR_FCM_CSCT \
  420. | OR_FCM_CST \
  421. | OR_FCM_CHT \
  422. | OR_FCM_SCY_1 \
  423. | OR_FCM_TRLX \
  424. | OR_FCM_EHTR)
  425. #else
  426. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
  427. | OR_FCM_CSCT \
  428. | OR_FCM_CST \
  429. | OR_FCM_CHT \
  430. | OR_FCM_SCY_1 \
  431. | OR_FCM_TRLX \
  432. | OR_FCM_EHTR)
  433. #endif
  434. #endif /* CONFIG_NAND_FSL_ELBC */
  435. #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  436. #define CONFIG_SYS_INIT_RAM_LOCK
  437. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  438. #ifdef CONFIG_PHYS_64BIT
  439. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  440. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  441. /* The assembler doesn't like typecast */
  442. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  443. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  444. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  445. #else
  446. /* Initial L1 address */
  447. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  448. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  449. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  450. #endif
  451. /* Size of used area in RAM */
  452. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  453. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  454. GENERATED_GBL_DATA_SIZE)
  455. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  456. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  457. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
  458. #define CONFIG_SYS_CPLD_BASE 0xffa00000
  459. #ifdef CONFIG_PHYS_64BIT
  460. #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
  461. #else
  462. #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  463. #endif
  464. /* CPLD config size: 1Mb */
  465. #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
  466. BR_PS_8 | BR_V)
  467. #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
  468. #define CONFIG_SYS_PMC_BASE 0xff980000
  469. #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
  470. #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
  471. BR_PS_8 | BR_V)
  472. #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
  473. OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
  474. OR_GPCM_EAD)
  475. #ifdef CONFIG_NAND
  476. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  477. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  478. #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  479. #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  480. #else
  481. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  482. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  483. #ifdef CONFIG_NAND_FSL_ELBC
  484. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  485. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  486. #endif
  487. #endif
  488. #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
  489. #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
  490. /* Vsc7385 switch */
  491. #ifdef CONFIG_VSC7385_ENET
  492. #define CONFIG_SYS_VSC7385_BASE 0xffb00000
  493. #ifdef CONFIG_PHYS_64BIT
  494. #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
  495. #else
  496. #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
  497. #endif
  498. #define CONFIG_SYS_VSC7385_BR_PRELIM \
  499. (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
  500. #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
  501. OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
  502. OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
  503. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
  504. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
  505. /* The size of the VSC7385 firmware image */
  506. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  507. #endif
  508. /*
  509. * Config the L2 Cache as L2 SRAM
  510. */
  511. #if defined(CONFIG_SPL_BUILD)
  512. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  513. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  514. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  515. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  516. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  517. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  518. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
  519. #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
  520. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
  521. #if defined(CONFIG_P2020RDB)
  522. #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
  523. #else
  524. #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
  525. #endif
  526. #elif defined(CONFIG_NAND)
  527. #ifdef CONFIG_TPL_BUILD
  528. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  529. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  530. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  531. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  532. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  533. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  534. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  535. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  536. #else
  537. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  538. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  539. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  540. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
  541. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  542. #endif /* CONFIG_TPL_BUILD */
  543. #endif
  544. #endif
  545. /* Serial Port - controlled on board with jumper J8
  546. * open - index 2
  547. * shorted - index 1
  548. */
  549. #define CONFIG_CONS_INDEX 1
  550. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  551. #define CONFIG_SYS_NS16550
  552. #define CONFIG_SYS_NS16550_SERIAL
  553. #define CONFIG_SYS_NS16550_REG_SIZE 1
  554. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  555. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  556. #define CONFIG_NS16550_MIN_FUNCTIONS
  557. #endif
  558. #define CONFIG_SYS_BAUDRATE_TABLE \
  559. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  560. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  561. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  562. /* Use the HUSH parser */
  563. #define CONFIG_SYS_HUSH_PARSER
  564. /*
  565. * Pass open firmware flat tree
  566. */
  567. #define CONFIG_OF_LIBFDT
  568. #define CONFIG_OF_BOARD_SETUP
  569. #define CONFIG_OF_STDOUT_VIA_ALIAS
  570. /* new uImage format support */
  571. #define CONFIG_FIT
  572. #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  573. /* I2C */
  574. #define CONFIG_SYS_I2C
  575. #define CONFIG_SYS_I2C_FSL
  576. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  577. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  578. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  579. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  580. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  581. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  582. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  583. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  584. #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
  585. /*
  586. * I2C2 EEPROM
  587. */
  588. #undef CONFIG_ID_EEPROM
  589. #define CONFIG_RTC_PT7C4338
  590. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  591. #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
  592. /* enable read and write access to EEPROM */
  593. #define CONFIG_CMD_EEPROM
  594. #define CONFIG_SYS_I2C_MULTI_EEPROMS
  595. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  596. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  597. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  598. /*
  599. * eSPI - Enhanced SPI
  600. */
  601. #define CONFIG_HARD_SPI
  602. #define CONFIG_FSL_ESPI
  603. #if defined(CONFIG_SPI_FLASH)
  604. #define CONFIG_SPI_FLASH_SPANSION
  605. #define CONFIG_CMD_SF
  606. #define CONFIG_SF_DEFAULT_SPEED 10000000
  607. #define CONFIG_SF_DEFAULT_MODE 0
  608. #endif
  609. #if defined(CONFIG_PCI)
  610. /*
  611. * General PCI
  612. * Memory space is mapped 1-1, but I/O space must start from 0.
  613. */
  614. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  615. #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
  616. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  617. #ifdef CONFIG_PHYS_64BIT
  618. #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
  619. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  620. #else
  621. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  622. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  623. #endif
  624. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  625. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  626. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  627. #ifdef CONFIG_PHYS_64BIT
  628. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  629. #else
  630. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  631. #endif
  632. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  633. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  634. #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
  635. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  636. #ifdef CONFIG_PHYS_64BIT
  637. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  638. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  639. #else
  640. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  641. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  642. #endif
  643. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  644. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  645. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  646. #ifdef CONFIG_PHYS_64BIT
  647. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
  648. #else
  649. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  650. #endif
  651. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  652. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  653. #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
  654. #define CONFIG_CMD_PCI
  655. #define CONFIG_CMD_NET
  656. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  657. #define CONFIG_DOS_PARTITION
  658. #endif /* CONFIG_PCI */
  659. #if defined(CONFIG_TSEC_ENET)
  660. #define CONFIG_MII /* MII PHY management */
  661. #define CONFIG_TSEC1
  662. #define CONFIG_TSEC1_NAME "eTSEC1"
  663. #define CONFIG_TSEC2
  664. #define CONFIG_TSEC2_NAME "eTSEC2"
  665. #define CONFIG_TSEC3
  666. #define CONFIG_TSEC3_NAME "eTSEC3"
  667. #define TSEC1_PHY_ADDR 2
  668. #define TSEC2_PHY_ADDR 0
  669. #define TSEC3_PHY_ADDR 1
  670. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  671. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  672. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  673. #define TSEC1_PHYIDX 0
  674. #define TSEC2_PHYIDX 0
  675. #define TSEC3_PHYIDX 0
  676. #define CONFIG_ETHPRIME "eTSEC1"
  677. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  678. #define CONFIG_HAS_ETH0
  679. #define CONFIG_HAS_ETH1
  680. #define CONFIG_HAS_ETH2
  681. #endif /* CONFIG_TSEC_ENET */
  682. #ifdef CONFIG_QE
  683. /* QE microcode/firmware address */
  684. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  685. #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
  686. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  687. #endif /* CONFIG_QE */
  688. #ifdef CONFIG_P1025RDB
  689. /*
  690. * QE UEC ethernet configuration
  691. */
  692. #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
  693. #undef CONFIG_UEC_ETH
  694. #define CONFIG_PHY_MODE_NEED_CHANGE
  695. #define CONFIG_UEC_ETH1 /* ETH1 */
  696. #define CONFIG_HAS_ETH0
  697. #ifdef CONFIG_UEC_ETH1
  698. #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
  699. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
  700. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
  701. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  702. #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
  703. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  704. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  705. #endif /* CONFIG_UEC_ETH1 */
  706. #define CONFIG_UEC_ETH5 /* ETH5 */
  707. #define CONFIG_HAS_ETH1
  708. #ifdef CONFIG_UEC_ETH5
  709. #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
  710. #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
  711. #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
  712. #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
  713. #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
  714. #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  715. #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
  716. #endif /* CONFIG_UEC_ETH5 */
  717. #endif /* CONFIG_P1025RDB */
  718. /*
  719. * Environment
  720. */
  721. #ifdef CONFIG_SPIFLASH
  722. #define CONFIG_ENV_IS_IN_SPI_FLASH
  723. #define CONFIG_ENV_SPI_BUS 0
  724. #define CONFIG_ENV_SPI_CS 0
  725. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  726. #define CONFIG_ENV_SPI_MODE 0
  727. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  728. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  729. #define CONFIG_ENV_SECT_SIZE 0x10000
  730. #elif defined(CONFIG_SDCARD)
  731. #define CONFIG_ENV_IS_IN_MMC
  732. #define CONFIG_FSL_FIXED_MMC_LOCATION
  733. #define CONFIG_ENV_SIZE 0x2000
  734. #define CONFIG_SYS_MMC_ENV_DEV 0
  735. #elif defined(CONFIG_NAND)
  736. #ifdef CONFIG_TPL_BUILD
  737. #define CONFIG_ENV_SIZE 0x2000
  738. #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  739. #else
  740. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  741. #endif
  742. #define CONFIG_ENV_IS_IN_NAND
  743. #define CONFIG_ENV_OFFSET (1024 * 1024)
  744. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
  745. #elif defined(CONFIG_SYS_RAMBOOT)
  746. #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
  747. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  748. #define CONFIG_ENV_SIZE 0x2000
  749. #else
  750. #define CONFIG_ENV_IS_IN_FLASH
  751. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  752. #define CONFIG_ENV_SIZE 0x2000
  753. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  754. #endif
  755. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  756. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  757. /*
  758. * Command line configuration.
  759. */
  760. #include <config_cmd_default.h>
  761. #define CONFIG_CMD_IRQ
  762. #define CONFIG_CMD_PING
  763. #define CONFIG_CMD_I2C
  764. #define CONFIG_CMD_MII
  765. #define CONFIG_CMD_DATE
  766. #define CONFIG_CMD_ELF
  767. #define CONFIG_CMD_SETEXPR
  768. #define CONFIG_CMD_REGINFO
  769. /*
  770. * USB
  771. */
  772. #define CONFIG_HAS_FSL_DR_USB
  773. #if defined(CONFIG_HAS_FSL_DR_USB)
  774. #define CONFIG_USB_EHCI
  775. #ifdef CONFIG_USB_EHCI
  776. #define CONFIG_CMD_USB
  777. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  778. #define CONFIG_USB_EHCI_FSL
  779. #define CONFIG_USB_STORAGE
  780. #endif
  781. #endif
  782. #if defined(CONFIG_P1020RDB_PD)
  783. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  784. #endif
  785. #define CONFIG_MMC
  786. #ifdef CONFIG_MMC
  787. #define CONFIG_FSL_ESDHC
  788. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  789. #define CONFIG_CMD_MMC
  790. #define CONFIG_GENERIC_MMC
  791. #endif
  792. #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
  793. || defined(CONFIG_FSL_SATA)
  794. #define CONFIG_CMD_EXT2
  795. #define CONFIG_CMD_FAT
  796. #define CONFIG_DOS_PARTITION
  797. #endif
  798. #undef CONFIG_WATCHDOG /* watchdog disabled */
  799. /*
  800. * Miscellaneous configurable options
  801. */
  802. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  803. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  804. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  805. #if defined(CONFIG_CMD_KGDB)
  806. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  807. #else
  808. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  809. #endif
  810. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  811. /* Print Buffer Size */
  812. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  813. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  814. /*
  815. * For booting Linux, the board info and command line data
  816. * have to be in the first 64 MB of memory, since this is
  817. * the maximum mapped by the Linux kernel during initialization.
  818. */
  819. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
  820. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  821. #if defined(CONFIG_CMD_KGDB)
  822. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  823. #endif
  824. /*
  825. * Environment Configuration
  826. */
  827. #define CONFIG_HOSTNAME unknown
  828. #define CONFIG_ROOTPATH "/opt/nfsroot"
  829. #define CONFIG_BOOTFILE "uImage"
  830. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  831. /* default location for tftp and bootm */
  832. #define CONFIG_LOADADDR 1000000
  833. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  834. #define CONFIG_BOOTARGS /* the boot command will set bootargs */
  835. #define CONFIG_BAUDRATE 115200
  836. #ifdef __SW_BOOT_NOR
  837. #define __NOR_RST_CMD \
  838. norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
  839. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  840. #endif
  841. #ifdef __SW_BOOT_SPI
  842. #define __SPI_RST_CMD \
  843. spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
  844. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  845. #endif
  846. #ifdef __SW_BOOT_SD
  847. #define __SD_RST_CMD \
  848. sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
  849. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  850. #endif
  851. #ifdef __SW_BOOT_NAND
  852. #define __NAND_RST_CMD \
  853. nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
  854. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  855. #endif
  856. #ifdef __SW_BOOT_PCIE
  857. #define __PCIE_RST_CMD \
  858. pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
  859. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  860. #endif
  861. #define CONFIG_EXTRA_ENV_SETTINGS \
  862. "netdev=eth0\0" \
  863. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  864. "loadaddr=1000000\0" \
  865. "bootfile=uImage\0" \
  866. "tftpflash=tftpboot $loadaddr $uboot; " \
  867. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  868. "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  869. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
  870. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  871. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
  872. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
  873. "consoledev=ttyS0\0" \
  874. "ramdiskaddr=2000000\0" \
  875. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  876. "fdtaddr=c00000\0" \
  877. "bdev=sda1\0" \
  878. "jffs2nor=mtdblock3\0" \
  879. "norbootaddr=ef080000\0" \
  880. "norfdtaddr=ef040000\0" \
  881. "jffs2nand=mtdblock9\0" \
  882. "nandbootaddr=100000\0" \
  883. "nandfdtaddr=80000\0" \
  884. "ramdisk_size=120000\0" \
  885. "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
  886. "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
  887. __stringify(__NOR_RST_CMD)"\0" \
  888. __stringify(__SPI_RST_CMD)"\0" \
  889. __stringify(__SD_RST_CMD)"\0" \
  890. __stringify(__NAND_RST_CMD)"\0" \
  891. __stringify(__PCIE_RST_CMD)"\0"
  892. #define CONFIG_NFSBOOTCOMMAND \
  893. "setenv bootargs root=/dev/nfs rw " \
  894. "nfsroot=$serverip:$rootpath " \
  895. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  896. "console=$consoledev,$baudrate $othbootargs;" \
  897. "tftp $loadaddr $bootfile;" \
  898. "tftp $fdtaddr $fdtfile;" \
  899. "bootm $loadaddr - $fdtaddr"
  900. #define CONFIG_HDBOOT \
  901. "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  902. "console=$consoledev,$baudrate $othbootargs;" \
  903. "usb start;" \
  904. "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  905. "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  906. "bootm $loadaddr - $fdtaddr"
  907. #define CONFIG_USB_FAT_BOOT \
  908. "setenv bootargs root=/dev/ram rw " \
  909. "console=$consoledev,$baudrate $othbootargs " \
  910. "ramdisk_size=$ramdisk_size;" \
  911. "usb start;" \
  912. "fatload usb 0:2 $loadaddr $bootfile;" \
  913. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  914. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  915. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  916. #define CONFIG_USB_EXT2_BOOT \
  917. "setenv bootargs root=/dev/ram rw " \
  918. "console=$consoledev,$baudrate $othbootargs " \
  919. "ramdisk_size=$ramdisk_size;" \
  920. "usb start;" \
  921. "ext2load usb 0:4 $loadaddr $bootfile;" \
  922. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  923. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  924. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  925. #define CONFIG_NORBOOT \
  926. "setenv bootargs root=/dev/$jffs2nor rw " \
  927. "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
  928. "bootm $norbootaddr - $norfdtaddr"
  929. #define CONFIG_RAMBOOTCOMMAND \
  930. "setenv bootargs root=/dev/ram rw " \
  931. "console=$consoledev,$baudrate $othbootargs " \
  932. "ramdisk_size=$ramdisk_size;" \
  933. "tftp $ramdiskaddr $ramdiskfile;" \
  934. "tftp $loadaddr $bootfile;" \
  935. "tftp $fdtaddr $fdtfile;" \
  936. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  937. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  938. #endif /* __CONFIG_H */