mx31pdk.h 6.2 KB

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  1. /*
  2. * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
  3. *
  4. * (C) Copyright 2004
  5. * Texas Instruments.
  6. * Richard Woodruff <r-woodruff2@ti.com>
  7. * Kshitij Gupta <kshitij@ti.com>
  8. *
  9. * Configuration settings for the Freescale i.MX31 PDK board.
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. #ifndef __CONFIG_H
  14. #define __CONFIG_H
  15. #include <asm/arch/imx-regs.h>
  16. /* High Level Configuration Options */
  17. #define CONFIG_ARM1136 /* This is an arm1136 CPU core */
  18. #define CONFIG_MX31 /* in a mx31 */
  19. #define CONFIG_DISPLAY_CPUINFO
  20. #define CONFIG_DISPLAY_BOARDINFO
  21. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  22. #define CONFIG_SETUP_MEMORY_TAGS
  23. #define CONFIG_INITRD_TAG
  24. #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
  25. #define CONFIG_SPL 1
  26. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  27. #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
  28. #define CONFIG_SPL_MAX_SIZE 2048
  29. #define CONFIG_SPL_NAND_SUPPORT
  30. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  31. #define CONFIG_SPL_TEXT_BASE 0x87dc0000
  32. #define CONFIG_SYS_TEXT_BASE 0x87e00000
  33. #ifndef CONFIG_SPL_BUILD
  34. #define CONFIG_SKIP_LOWLEVEL_INIT
  35. #endif
  36. /*
  37. * Size of malloc() pool
  38. */
  39. #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
  40. /*
  41. * Hardware drivers
  42. */
  43. #define CONFIG_MXC_UART
  44. #define CONFIG_MXC_UART_BASE UART1_BASE
  45. #define CONFIG_MXC_GPIO
  46. #define CONFIG_HARD_SPI
  47. #define CONFIG_MXC_SPI
  48. #define CONFIG_DEFAULT_SPI_BUS 1
  49. #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
  50. /* PMIC Controller */
  51. #define CONFIG_POWER
  52. #define CONFIG_POWER_SPI
  53. #define CONFIG_POWER_FSL
  54. #define CONFIG_FSL_PMIC_BUS 1
  55. #define CONFIG_FSL_PMIC_CS 2
  56. #define CONFIG_FSL_PMIC_CLK 1000000
  57. #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
  58. #define CONFIG_FSL_PMIC_BITLEN 32
  59. #define CONFIG_RTC_MC13XXX
  60. /* allow to overwrite serial and ethaddr */
  61. #define CONFIG_ENV_OVERWRITE
  62. #define CONFIG_CONS_INDEX 1
  63. #define CONFIG_BAUDRATE 115200
  64. /***********************************************************
  65. * Command definition
  66. ***********************************************************/
  67. #include <config_cmd_default.h>
  68. #define CONFIG_CMD_MII
  69. #define CONFIG_CMD_PING
  70. #define CONFIG_CMD_DHCP
  71. #define CONFIG_CMD_SPI
  72. #define CONFIG_CMD_DATE
  73. #define CONFIG_CMD_NAND
  74. #define CONFIG_CMD_BOOTZ
  75. /*
  76. * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
  77. * that CFG_NO_FLASH is undefined).
  78. */
  79. #undef CONFIG_CMD_IMLS
  80. #define CONFIG_BOARD_LATE_INIT
  81. #define CONFIG_BOOTDELAY 1
  82. #define CONFIG_EXTRA_ENV_SETTINGS \
  83. "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
  84. "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
  85. "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
  86. "bootcmd=run bootcmd_net\0" \
  87. "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
  88. "tftpboot 0x81000000 uImage-mx31; bootm\0" \
  89. "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
  90. "nand erase 0x0 0x40000; " \
  91. "nand write 0x81000000 0x0 0x40000\0"
  92. #define CONFIG_SMC911X
  93. #define CONFIG_SMC911X_BASE 0xB6000000
  94. #define CONFIG_SMC911X_32_BIT
  95. /*
  96. * Miscellaneous configurable options
  97. */
  98. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  99. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  100. /* Print Buffer Size */
  101. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  102. sizeof(CONFIG_SYS_PROMPT)+16)
  103. /* max number of command args */
  104. #define CONFIG_SYS_MAXARGS 16
  105. /* Boot Argument Buffer Size */
  106. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  107. /* memtest works on */
  108. #define CONFIG_SYS_MEMTEST_START 0x80000000
  109. #define CONFIG_SYS_MEMTEST_END 0x80010000
  110. /* default load address */
  111. #define CONFIG_SYS_LOAD_ADDR 0x81000000
  112. #define CONFIG_CMDLINE_EDITING
  113. /*-----------------------------------------------------------------------
  114. * Physical Memory Map
  115. */
  116. #define CONFIG_NR_DRAM_BANKS 1
  117. #define PHYS_SDRAM_1 CSD0_BASE
  118. #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
  119. #define CONFIG_BOARD_EARLY_INIT_F
  120. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  121. #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  122. #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
  123. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  124. GENERATED_GBL_DATA_SIZE)
  125. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  126. CONFIG_SYS_INIT_RAM_SIZE)
  127. /*-----------------------------------------------------------------------
  128. * FLASH and environment organization
  129. */
  130. /* No NOR flash present */
  131. #define CONFIG_SYS_NO_FLASH
  132. #define CONFIG_ENV_IS_IN_NAND
  133. #define CONFIG_ENV_OFFSET 0x40000
  134. #define CONFIG_ENV_OFFSET_REDUND 0x60000
  135. #define CONFIG_ENV_SIZE (128 * 1024)
  136. /*
  137. * NAND driver
  138. */
  139. #define CONFIG_NAND_MXC
  140. #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
  141. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  142. #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
  143. #define CONFIG_MXC_NAND_HWECC
  144. #define CONFIG_SYS_NAND_LARGEPAGE
  145. /* NAND configuration for the NAND_SPL */
  146. /* Start copying real U-boot from the second page */
  147. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  148. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
  149. /* Load U-Boot to this address */
  150. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  151. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  152. #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
  153. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  154. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  155. #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
  156. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  157. /* Configuration of lowlevel_init.S (clocks and SDRAM) */
  158. #define CCM_CCMR_SETUP 0x074B0BF5
  159. #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
  160. PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
  161. PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
  162. PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
  163. #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
  164. PLL_MFN(12))
  165. #define ESDMISC_MDDR_SETUP 0x00000004
  166. #define ESDMISC_MDDR_RESET_DL 0x0000000c
  167. #define ESDCFG0_MDDR_SETUP 0x006ac73a
  168. #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
  169. #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
  170. ESDCTL_DSIZ(2) | ESDCTL_BL(1))
  171. #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
  172. #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
  173. #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
  174. #define ESDCTL_RW ESDCTL_SETTINGS
  175. #endif /* __CONFIG_H */