lwmon5.h 25 KB

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  1. /*
  2. * (C) Copyright 2007-2013
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * lwmon5.h - configuration for lwmon5 board
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * Liebherr extra version info
  14. */
  15. #define CONFIG_IDENT_STRING " - v2.0"
  16. /*
  17. * High Level Configuration Options
  18. */
  19. #define CONFIG_LWMON5 1 /* Board is lwmon5 */
  20. #define CONFIG_440EPX 1 /* Specific PPC440EPx */
  21. #define CONFIG_440 1 /* ... PPC440 family */
  22. #ifdef CONFIG_LCD4_LWMON5
  23. #define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
  24. #define CONFIG_HOSTNAME lcd4_lwmon5
  25. #else
  26. #define CONFIG_SYS_TEXT_BASE 0xFFF80000
  27. #define CONFIG_HOSTNAME lwmon5
  28. #endif
  29. #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
  30. #define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
  31. #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
  32. #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
  33. #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
  34. #define CONFIG_MISC_INIT_R /* Call misc_init_r */
  35. #define CONFIG_BOARD_RESET /* Call board_reset */
  36. /*
  37. * Base addresses -- Note these are effective addresses where the
  38. * actual resources get mapped (not physical addresses)
  39. */
  40. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
  41. #define CONFIG_SYS_MONITOR_LEN 0x80000
  42. #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
  43. #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
  44. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
  45. #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
  46. #define CONFIG_SYS_LIME_BASE_0 0xc0000000
  47. #define CONFIG_SYS_LIME_BASE_1 0xc1000000
  48. #define CONFIG_SYS_LIME_BASE_2 0xc2000000
  49. #define CONFIG_SYS_LIME_BASE_3 0xc3000000
  50. #define CONFIG_SYS_FPGA_BASE_0 0xc4000000
  51. #define CONFIG_SYS_FPGA_BASE_1 0xc4200000
  52. #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
  53. #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
  54. #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
  55. #define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
  56. #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
  57. #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
  58. #ifndef CONFIG_LCD4_LWMON5
  59. #define CONFIG_SYS_USB2D0_BASE 0xe0000100
  60. #define CONFIG_SYS_USB_DEVICE 0xe0000000
  61. #define CONFIG_SYS_USB_HOST 0xe0000400
  62. #endif
  63. /*
  64. * Initial RAM & stack pointer
  65. *
  66. * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
  67. * the POST_WORD from OCM to a 440EPx register that preserves it's
  68. * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
  69. * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
  70. */
  71. #ifndef CONFIG_LCD4_LWMON5
  72. #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
  73. #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
  74. #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
  75. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  76. GENERATED_GBL_DATA_SIZE)
  77. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  78. #else
  79. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
  80. #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
  81. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  82. GENERATED_GBL_DATA_SIZE)
  83. #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  84. #endif
  85. /* unused GPT0 COMP reg */
  86. #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
  87. #define CONFIG_SYS_OCM_SIZE (16 << 10)
  88. /* 440EPx errata CHIP 11: don't use last 4kbytes */
  89. #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
  90. /* Additional registers for watchdog timer post test */
  91. #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
  92. #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
  93. #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
  94. #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
  95. #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
  96. #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
  97. #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
  98. #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
  99. #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
  100. #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
  101. /*
  102. * Serial Port
  103. */
  104. #define CONFIG_CONS_INDEX 2 /* Use UART1 */
  105. #define CONFIG_SYS_NS16550
  106. #define CONFIG_SYS_NS16550_SERIAL
  107. #define CONFIG_SYS_NS16550_REG_SIZE 1
  108. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  109. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
  110. #define CONFIG_BAUDRATE 115200
  111. #define CONFIG_SYS_BAUDRATE_TABLE \
  112. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  113. /*
  114. * Environment
  115. */
  116. #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
  117. /*
  118. * FLASH related
  119. */
  120. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  121. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  122. #define CONFIG_SYS_FLASH0 0xFC000000
  123. #define CONFIG_SYS_FLASH1 0xF8000000
  124. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
  125. #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
  126. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
  127. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  128. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  129. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
  130. #define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
  131. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  132. #define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
  133. #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
  134. #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
  135. #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
  136. /* Address and size of Redundant Environment Sector */
  137. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
  138. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  139. /*
  140. * DDR SDRAM
  141. */
  142. #define CONFIG_SYS_MBYTES_SDRAM 256
  143. #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
  144. #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
  145. #ifndef CONFIG_LCD4_LWMON5
  146. #define CONFIG_DDR_ECC /* enable ECC */
  147. #endif
  148. #ifndef CONFIG_LCD4_LWMON5
  149. /* POST support */
  150. #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
  151. CONFIG_SYS_POST_CPU | \
  152. CONFIG_SYS_POST_ECC | \
  153. CONFIG_SYS_POST_ETHER | \
  154. CONFIG_SYS_POST_FPU | \
  155. CONFIG_SYS_POST_I2C | \
  156. CONFIG_SYS_POST_MEMORY | \
  157. CONFIG_SYS_POST_OCM | \
  158. CONFIG_SYS_POST_RTC | \
  159. CONFIG_SYS_POST_SPR | \
  160. CONFIG_SYS_POST_UART | \
  161. CONFIG_SYS_POST_SYSMON | \
  162. CONFIG_SYS_POST_WATCHDOG | \
  163. CONFIG_SYS_POST_DSP | \
  164. CONFIG_SYS_POST_BSPEC1 | \
  165. CONFIG_SYS_POST_BSPEC2 | \
  166. CONFIG_SYS_POST_BSPEC3 | \
  167. CONFIG_SYS_POST_BSPEC4 | \
  168. CONFIG_SYS_POST_BSPEC5)
  169. /* Define here the base-addresses of the UARTs to test in POST */
  170. #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
  171. CONFIG_SYS_NS16550_COM2 }
  172. #define CONFIG_POST_UART { \
  173. "UART test", \
  174. "uart", \
  175. "This test verifies the UART operation.", \
  176. POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
  177. &uart_post_test, \
  178. NULL, \
  179. NULL, \
  180. CONFIG_SYS_POST_UART \
  181. }
  182. #define CONFIG_POST_WATCHDOG { \
  183. "Watchdog timer test", \
  184. "watchdog", \
  185. "This test checks the watchdog timer.", \
  186. POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
  187. &lwmon5_watchdog_post_test, \
  188. NULL, \
  189. NULL, \
  190. CONFIG_SYS_POST_WATCHDOG \
  191. }
  192. #define CONFIG_POST_BSPEC1 { \
  193. "dsPIC init test", \
  194. "dspic_init", \
  195. "This test returns result of dsPIC READY test run earlier.", \
  196. POST_RAM | POST_ALWAYS, \
  197. &dspic_init_post_test, \
  198. NULL, \
  199. NULL, \
  200. CONFIG_SYS_POST_BSPEC1 \
  201. }
  202. #define CONFIG_POST_BSPEC2 { \
  203. "dsPIC test", \
  204. "dspic", \
  205. "This test gets result of dsPIC POST and dsPIC version.", \
  206. POST_RAM | POST_ALWAYS, \
  207. &dspic_post_test, \
  208. NULL, \
  209. NULL, \
  210. CONFIG_SYS_POST_BSPEC2 \
  211. }
  212. #define CONFIG_POST_BSPEC3 { \
  213. "FPGA test", \
  214. "fpga", \
  215. "This test checks FPGA registers and memory.", \
  216. POST_RAM | POST_ALWAYS | POST_MANUAL, \
  217. &fpga_post_test, \
  218. NULL, \
  219. NULL, \
  220. CONFIG_SYS_POST_BSPEC3 \
  221. }
  222. #define CONFIG_POST_BSPEC4 { \
  223. "GDC test", \
  224. "gdc", \
  225. "This test checks GDC registers and memory.", \
  226. POST_RAM | POST_ALWAYS | POST_MANUAL,\
  227. &gdc_post_test, \
  228. NULL, \
  229. NULL, \
  230. CONFIG_SYS_POST_BSPEC4 \
  231. }
  232. #define CONFIG_POST_BSPEC5 { \
  233. "SYSMON1 test", \
  234. "sysmon1", \
  235. "This test checks GPIO_62_EPX pin indicating power failure.", \
  236. POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
  237. &sysmon1_post_test, \
  238. NULL, \
  239. NULL, \
  240. CONFIG_SYS_POST_BSPEC5 \
  241. }
  242. #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
  243. #define CONFIG_LOGBUFFER
  244. /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
  245. #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
  246. #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
  247. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
  248. #endif
  249. /*
  250. * I2C
  251. */
  252. #define CONFIG_SYS_I2C
  253. #define CONFIG_SYS_I2C_PPC4XX
  254. #define CONFIG_SYS_I2C_PPC4XX_CH0
  255. #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
  256. #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
  257. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
  258. #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
  259. #define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
  260. #define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
  261. #define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
  262. #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
  263. #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
  264. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
  265. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
  266. /* 64 byte page write mode using*/
  267. /* last 6 bits of the address */
  268. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  269. #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
  270. #define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
  271. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
  272. #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
  273. #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
  274. #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
  275. CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
  276. CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
  277. CONFIG_SYS_I2C_DSPIC_ADDR, \
  278. CONFIG_SYS_I2C_DSPIC_2_ADDR, \
  279. CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
  280. CONFIG_SYS_I2C_DSPIC_IO_ADDR }
  281. /*
  282. * Pass open firmware flat tree
  283. */
  284. #define CONFIG_OF_LIBFDT
  285. #define CONFIG_OF_BOARD_SETUP
  286. /* Update size in "reg" property of NOR FLASH device tree nodes */
  287. #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
  288. #define CONFIG_FIT /* enable FIT image support */
  289. #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
  290. #define CONFIG_PREBOOT "setenv bootdelay 15"
  291. #undef CONFIG_BOOTARGS
  292. #define CONFIG_EXTRA_ENV_SETTINGS \
  293. "hostname=lwmon5\0" \
  294. "netdev=eth0\0" \
  295. "unlock=yes\0" \
  296. "logversion=2\0" \
  297. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  298. "nfsroot=${serverip}:${rootpath}\0" \
  299. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  300. "addip=setenv bootargs ${bootargs} " \
  301. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  302. ":${hostname}:${netdev}:off panic=1\0" \
  303. "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
  304. "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
  305. "flash_nfs=run nfsargs addip addtty addmisc;" \
  306. "bootm ${kernel_addr}\0" \
  307. "flash_self=run ramargs addip addtty addmisc;" \
  308. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  309. "net_nfs=tftp 200000 ${bootfile};" \
  310. "run nfsargs addip addtty addmisc;bootm\0" \
  311. "rootpath=/opt/eldk/ppc_4xxFP\0" \
  312. "bootfile=/tftpboot/lwmon5/uImage\0" \
  313. "kernel_addr=FC000000\0" \
  314. "ramdisk_addr=FC180000\0" \
  315. "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
  316. "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
  317. "cp.b 200000 FFF80000 80000\0" \
  318. "upd=run load update\0" \
  319. "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
  320. "autoscr 200000\0" \
  321. ""
  322. #define CONFIG_BOOTCOMMAND "run flash_self"
  323. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  324. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  325. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  326. #define CONFIG_PPC4xx_EMAC
  327. #define CONFIG_IBM_EMAC4_V4 1
  328. #define CONFIG_MII 1 /* MII PHY management */
  329. #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
  330. #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
  331. #define CONFIG_PHY_RESET_DELAY 300
  332. #define CONFIG_HAS_ETH0
  333. #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
  334. #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
  335. #define CONFIG_PHY1_ADDR 1
  336. /* Video console */
  337. #define CONFIG_VIDEO
  338. #define CONFIG_VIDEO_MB862xx
  339. #define CONFIG_VIDEO_MB862xx_ACCEL
  340. #define CONFIG_CFB_CONSOLE
  341. #define CONFIG_VIDEO_LOGO
  342. #define CONFIG_CONSOLE_EXTRA_INFO
  343. #define VIDEO_FB_16BPP_PIXEL_SWAP
  344. #define VIDEO_FB_16BPP_WORD_SWAP
  345. #define CONFIG_VGA_AS_SINGLE_DEVICE
  346. #define CONFIG_VIDEO_SW_CURSOR
  347. #define CONFIG_SPLASH_SCREEN
  348. #ifndef CONFIG_LCD4_LWMON5
  349. /*
  350. * USB/EHCI
  351. */
  352. #define CONFIG_USB_EHCI /* Enable EHCI USB support */
  353. #define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
  354. #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
  355. #define CONFIG_EHCI_MMIO_BIG_ENDIAN
  356. #define CONFIG_EHCI_DESC_BIG_ENDIAN
  357. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
  358. #define CONFIG_USB_STORAGE
  359. /* Partitions */
  360. #define CONFIG_MAC_PARTITION
  361. #define CONFIG_DOS_PARTITION
  362. #define CONFIG_ISO_PARTITION
  363. #endif
  364. /*
  365. * BOOTP options
  366. */
  367. #define CONFIG_BOOTP_BOOTFILESIZE
  368. #define CONFIG_BOOTP_BOOTPATH
  369. #define CONFIG_BOOTP_GATEWAY
  370. #define CONFIG_BOOTP_HOSTNAME
  371. /*
  372. * Command line configuration.
  373. */
  374. #include <config_cmd_default.h>
  375. #define CONFIG_CMD_ASKENV
  376. #define CONFIG_CMD_DATE
  377. #define CONFIG_CMD_DHCP
  378. #define CONFIG_CMD_DIAG
  379. #define CONFIG_CMD_EEPROM
  380. #define CONFIG_CMD_ELF
  381. #define CONFIG_CMD_FAT
  382. #define CONFIG_CMD_I2C
  383. #define CONFIG_CMD_IRQ
  384. #define CONFIG_CMD_MII
  385. #define CONFIG_CMD_NET
  386. #define CONFIG_CMD_NFS
  387. #define CONFIG_CMD_PING
  388. #define CONFIG_CMD_REGINFO
  389. #define CONFIG_CMD_SDRAM
  390. #ifdef CONFIG_VIDEO
  391. #define CONFIG_CMD_BMP
  392. #endif
  393. #ifndef CONFIG_LCD4_LWMON5
  394. #ifdef CONFIG_440EPX
  395. #define CONFIG_CMD_USB
  396. #endif
  397. #endif
  398. /*
  399. * Miscellaneous configurable options
  400. */
  401. #define CONFIG_SUPPORT_VFAT
  402. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  403. #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
  404. #if defined(CONFIG_CMD_KGDB)
  405. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  406. #else
  407. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  408. #endif
  409. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  410. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  411. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  412. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  413. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  414. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  415. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  416. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  417. #define CONFIG_LOOPW 1 /* enable loopw command */
  418. #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
  419. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  420. #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
  421. #ifndef CONFIG_LCD4_LWMON5
  422. #ifndef DEBUG
  423. #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
  424. #endif
  425. #define CONFIG_WD_PERIOD 40000 /* in usec */
  426. #define CONFIG_WD_MAX_RATE 66600 /* in ticks */
  427. #endif
  428. /*
  429. * For booting Linux, the board info and command line data
  430. * have to be in the first 16 MB of memory, since this is
  431. * the maximum mapped by the 40x Linux kernel during initialization.
  432. */
  433. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
  434. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  435. /*
  436. * External Bus Controller (EBC) Setup
  437. */
  438. #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
  439. /* Memory Bank 0 (NOR-FLASH) initialization */
  440. #define CONFIG_SYS_EBC_PB0AP 0x03000280
  441. #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
  442. /* Memory Bank 1 (Lime) initialization */
  443. #define CONFIG_SYS_EBC_PB1AP 0x01004380
  444. #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
  445. /* Memory Bank 2 (FPGA) initialization */
  446. #define CONFIG_SYS_EBC_PB2AP 0x01004400
  447. #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
  448. /* Memory Bank 3 (FPGA2) initialization */
  449. #define CONFIG_SYS_EBC_PB3AP 0x01004400
  450. #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
  451. #define CONFIG_SYS_EBC_CFG 0xb8400000
  452. /*
  453. * Graphics (Fujitsu Lime)
  454. */
  455. /* SDRAM Clock frequency adjustment register */
  456. #define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
  457. #if 1 /* 133MHz is not tested enough, use 100MHz for now */
  458. /* Lime Clock frequency is to set 100MHz */
  459. #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
  460. #else
  461. /* Lime Clock frequency for 133MHz */
  462. #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
  463. #endif
  464. /* SDRAM Parameter register */
  465. #define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
  466. /*
  467. * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
  468. * and pixel flare on display when 133MHz was configured. According to
  469. * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
  470. * Grade
  471. */
  472. #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
  473. #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
  474. #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
  475. #else
  476. #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
  477. #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
  478. #endif
  479. /*
  480. * GPIO Setup
  481. */
  482. #define CONFIG_SYS_GPIO_PHY1_RST 12
  483. #define CONFIG_SYS_GPIO_FLASH_WP 14
  484. #define CONFIG_SYS_GPIO_PHY0_RST 22
  485. #define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
  486. #define CONFIG_SYS_GPIO_DSPIC_READY 51
  487. #define CONFIG_SYS_GPIO_CAN_ENABLE 53
  488. #define CONFIG_SYS_GPIO_LSB_ENABLE 54
  489. #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
  490. #define CONFIG_SYS_GPIO_HIGHSIDE 56
  491. #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
  492. #define CONFIG_SYS_GPIO_BOARD_RESET 58
  493. #define CONFIG_SYS_GPIO_LIME_S 59
  494. #define CONFIG_SYS_GPIO_LIME_RST 60
  495. #define CONFIG_SYS_GPIO_SYSMON_STATUS 62
  496. #define CONFIG_SYS_GPIO_WATCHDOG 63
  497. /* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
  498. #ifdef CONFIG_LCD4_LWMON5
  499. #define GPIO49_VAL 0
  500. #else
  501. #define GPIO49_VAL 1
  502. #endif
  503. /*
  504. * PPC440 GPIO Configuration
  505. */
  506. #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
  507. { \
  508. /* GPIO Core 0 */ \
  509. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
  510. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
  511. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
  512. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
  513. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
  514. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
  515. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
  516. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
  517. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
  518. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
  519. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
  520. {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
  521. {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
  522. {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
  523. {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
  524. {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
  525. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
  526. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
  527. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
  528. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
  529. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
  530. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
  531. {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
  532. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
  533. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
  534. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
  535. {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
  536. {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
  537. {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
  538. {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
  539. {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
  540. {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
  541. }, \
  542. { \
  543. /* GPIO Core 1 */ \
  544. {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
  545. {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
  546. {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
  547. {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
  548. {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
  549. {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
  550. {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
  551. {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
  552. {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
  553. {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
  554. {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
  555. {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
  556. {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
  557. {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
  558. {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
  559. {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
  560. {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
  561. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
  562. {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
  563. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
  564. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
  565. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
  566. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
  567. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
  568. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
  569. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
  570. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
  571. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
  572. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
  573. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
  574. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
  575. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
  576. } \
  577. }
  578. #if defined(CONFIG_CMD_KGDB)
  579. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  580. #endif
  581. /*
  582. * SPL related defines
  583. */
  584. #ifdef CONFIG_LCD4_LWMON5
  585. #define CONFIG_SPL 1
  586. #define CONFIG_SPL_FRAMEWORK
  587. #define CONFIG_SPL_BOARD_INIT
  588. #define CONFIG_SPL_NOR_SUPPORT
  589. #define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
  590. #define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
  591. #define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
  592. #define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx"
  593. #define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds"
  594. #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
  595. #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
  596. #define CONFIG_SPL_SERIAL_SUPPORT
  597. /* Place BSS for SPL near end of SDRAM */
  598. #define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20)
  599. #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
  600. #define CONFIG_SPL_OS_BOOT
  601. /* Place patched DT blob (fdt) at this address */
  602. #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
  603. #define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin"
  604. /* Settings for real U-Boot to be loaded from NOR flash */
  605. #define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN)
  606. #define CONFIG_SYS_UBOOT_START 0x01002100
  607. #define CONFIG_SYS_OS_BASE 0xf8000000
  608. #define CONFIG_SYS_FDT_BASE 0xf87c0000
  609. #endif
  610. #endif /* __CONFIG_H */