ipam390.h 10 KB

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  1. /*
  2. * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
  3. * Based on:
  4. * U-Boot:include/configs/da850evm.h
  5. *
  6. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  7. *
  8. * Based on davinci_dvevm.h. Original Copyrights follow:
  9. *
  10. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  11. *
  12. * SPDX-License-Identifier: GPL-2.0+
  13. */
  14. #ifndef __CONFIG_H
  15. #define __CONFIG_H
  16. /*
  17. * Board
  18. */
  19. #define CONFIG_DRIVER_TI_EMAC
  20. #define CONFIG_BARIX_IPAM390
  21. /*
  22. * SoC Configuration
  23. */
  24. #define CONFIG_MACH_DAVINCI_DA850_EVM
  25. #define CONFIG_ARM926EJS /* arm926ejs CPU core */
  26. #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
  27. #define CONFIG_SOC_DA850 /* TI DA850 SoC */
  28. #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  29. #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
  30. #define CONFIG_SYS_OSCIN_FREQ 24000000
  31. #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
  32. #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
  33. #define CONFIG_SYS_DA850_PLL_INIT
  34. #define CONFIG_SYS_DA850_DDR_INIT
  35. #define CONFIG_SYS_TEXT_BASE 0xc1080000
  36. /*
  37. * Memory Info
  38. */
  39. #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
  40. #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  41. #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
  42. #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  43. /* memtest start addr */
  44. #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
  45. /* memtest will be run on 16MB */
  46. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
  47. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  48. #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
  49. DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
  50. DAVINCI_SYSCFG_SUSPSRC_UART2 | \
  51. DAVINCI_SYSCFG_SUSPSRC_UART0 | \
  52. DAVINCI_SYSCFG_SUSPSRC_EMAC)
  53. /*
  54. * PLL configuration
  55. */
  56. #define CONFIG_SYS_DV_CLKMODE 0
  57. #define CONFIG_SYS_DA850_PLL0_POSTDIV 1
  58. #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
  59. #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
  60. #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
  61. #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
  62. #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
  63. #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
  64. #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
  65. #define CONFIG_SYS_DA850_PLL1_POSTDIV 1
  66. #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
  67. #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
  68. #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
  69. #define CONFIG_SYS_DA850_PLL0_PLLM 24
  70. #define CONFIG_SYS_DA850_PLL1_PLLM 24
  71. /*
  72. * DDR2 memory configuration
  73. */
  74. #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  75. DV_DDR_PHY_EXT_STRBEN | \
  76. (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  77. #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498
  78. #define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004
  79. #define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020
  80. #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
  81. (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \
  82. (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
  83. (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
  84. (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
  85. (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
  86. (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
  87. (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
  88. (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  89. #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
  90. (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
  91. (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
  92. (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
  93. (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
  94. (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
  95. (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
  96. (2 << DV_DDR_SDTMR2_CKE_SHIFT))
  97. #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
  98. (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
  99. (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
  100. (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
  101. (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
  102. (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
  103. (2 << DV_DDR_SDCR_CL_SHIFT) | \
  104. (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
  105. (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  106. #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
  107. DAVINCI_ABCR_WSTROBE(2) | \
  108. DAVINCI_ABCR_WHOLD(0) | \
  109. DAVINCI_ABCR_RSETUP(1) | \
  110. DAVINCI_ABCR_RSTROBE(2) | \
  111. DAVINCI_ABCR_RHOLD(1) | \
  112. DAVINCI_ABCR_TA(0) | \
  113. DAVINCI_ABCR_ASIZE_8BIT)
  114. /*
  115. * Serial Driver info
  116. */
  117. #define CONFIG_SYS_NS16550
  118. #define CONFIG_SYS_NS16550_SERIAL
  119. #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
  120. #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
  121. #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
  122. #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
  123. #define CONFIG_BAUDRATE 115200 /* Default baud rate */
  124. /*
  125. * Flash & Environment
  126. */
  127. #define CONFIG_NAND_DAVINCI
  128. #define CONFIG_SYS_NO_FLASH
  129. #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
  130. #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
  131. #define CONFIG_ENV_SIZE (128 << 10)
  132. #define CONFIG_SYS_NAND_USE_FLASH_BBT
  133. #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  134. #define CONFIG_SYS_NAND_PAGE_2K
  135. #define CONFIG_SYS_NAND_CS 3
  136. #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
  137. #define CONFIG_SYS_NAND_MASK_CLE 0x10
  138. #define CONFIG_SYS_NAND_MASK_ALE 0x8
  139. #undef CONFIG_SYS_NAND_HW_ECC
  140. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  141. #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
  142. #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
  143. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  144. #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
  145. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
  146. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  147. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000
  148. #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
  149. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  150. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
  151. CONFIG_SYS_NAND_U_BOOT_SIZE - \
  152. CONFIG_SYS_MALLOC_LEN - \
  153. GENERATED_GBL_DATA_SIZE)
  154. #define CONFIG_SYS_NAND_ECCPOS { \
  155. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
  156. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
  157. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
  158. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63}
  159. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  160. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  161. #define CONFIG_SYS_NAND_ECCSIZE 512
  162. #define CONFIG_SYS_NAND_ECCBYTES 10
  163. #define CONFIG_SYS_NAND_OOBSIZE 64
  164. #define CONFIG_SPL_NAND_SUPPORT
  165. #define CONFIG_SPL_NAND_BASE
  166. #define CONFIG_SPL_NAND_DRIVERS
  167. #define CONFIG_SPL_NAND_ECC
  168. #define CONFIG_SPL_NAND_SIMPLE
  169. #define CONFIG_SPL_NAND_LOAD
  170. /*
  171. * Network & Ethernet Configuration
  172. */
  173. #ifdef CONFIG_DRIVER_TI_EMAC
  174. #define CONFIG_DRIVER_TI_EMAC_USE_RMII
  175. #define CONFIG_BOOTP_DEFAULT
  176. #define CONFIG_BOOTP_DNS
  177. #define CONFIG_BOOTP_DNS2
  178. #define CONFIG_BOOTP_SEND_HOSTNAME
  179. #define CONFIG_NET_RETRY_COUNT 10
  180. #endif
  181. /*
  182. * U-Boot general configuration
  183. */
  184. #define CONFIG_MISC_INIT_R
  185. #define CONFIG_BOARD_EARLY_INIT_F
  186. #define CONFIG_BOOTFILE "uImage" /* Boot file name */
  187. #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
  188. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  189. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  190. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  191. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
  192. #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
  193. #define CONFIG_VERSION_VARIABLE
  194. #define CONFIG_AUTO_COMPLETE
  195. #define CONFIG_SYS_HUSH_PARSER
  196. #define CONFIG_CMDLINE_EDITING
  197. #define CONFIG_SYS_LONGHELP
  198. #define CONFIG_CRC32_VERIFY
  199. #define CONFIG_MX_CYCLIC
  200. /*
  201. * Linux Information
  202. */
  203. #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
  204. #define CONFIG_HWCONFIG /* enable hwconfig */
  205. #define CONFIG_CMDLINE_TAG
  206. #define CONFIG_REVISION_TAG
  207. #define CONFIG_SETUP_MEMORY_TAGS
  208. #define CONFIG_BOOTDELAY 2
  209. #define CONFIG_EXTRA_ENV_SETTINGS \
  210. "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
  211. "root=/dev/mtdblock5 rw noinitrd " \
  212. "rootfstype=jffs2 noinitrd\0" \
  213. "hwconfig=dsp:wake=yes\0" \
  214. "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
  215. "bootfile=uImage\0" \
  216. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  217. "mtddevname=uboot-env\0" \
  218. "mtddevnum=0\0" \
  219. "mtdids=" MTDIDS_DEFAULT "\0" \
  220. "mtdparts=" MTDPARTS_DEFAULT "\0" \
  221. "u-boot=/tftpboot/ipam390/u-boot.ais\0" \
  222. "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
  223. "nand write c0000000 20000 ${filesize}\0" \
  224. "setbootparms=nand read c0100000 200000 400000;" \
  225. "run defbootargs addmtd;" \
  226. "spl export atags c0100000;" \
  227. "nand erase.part bootparms;" \
  228. "nand write c0000100 180000 20000\0" \
  229. "\0"
  230. /*
  231. * U-Boot commands
  232. */
  233. #include <config_cmd_default.h>
  234. #define CONFIG_CMD_ENV
  235. #define CONFIG_CMD_ASKENV
  236. #define CONFIG_CMD_DHCP
  237. #define CONFIG_CMD_DIAG
  238. #define CONFIG_CMD_MII
  239. #define CONFIG_CMD_PING
  240. #define CONFIG_CMD_SAVES
  241. #define CONFIG_CMD_MEMORY
  242. #ifdef CONFIG_CMD_BDI
  243. #define CONFIG_CLOCKS
  244. #endif
  245. #ifndef CONFIG_DRIVER_TI_EMAC
  246. #undef CONFIG_CMD_NET
  247. #undef CONFIG_CMD_DHCP
  248. #undef CONFIG_CMD_MII
  249. #undef CONFIG_CMD_PING
  250. #endif
  251. #define CONFIG_CMD_NAND
  252. #define CONFIG_CMD_NAND_TRIMFFS
  253. #define CONFIG_CMD_MTDPARTS
  254. #define CONFIG_MTD_DEVICE
  255. #define CONFIG_MTD_PARTITIONS
  256. #define CONFIG_LZO
  257. #define CONFIG_RBTREE
  258. #define CONFIG_CMD_UBI
  259. #define CONFIG_CMD_UBIFS
  260. #define MTDIDS_NAME_STR "davinci_nand.0"
  261. #define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
  262. #define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
  263. "128k(u-boot-env)," \
  264. "1408k(u-boot)," \
  265. "128k(bootparms)," \
  266. "384k(factory-info)," \
  267. "4M(kernel)," \
  268. "-(rootfs)"
  269. /* defines for SPL */
  270. #define CONFIG_SPL 1
  271. #define CONFIG_SPL_FRAMEWORK
  272. #define CONFIG_SPL_BOARD_INIT
  273. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
  274. CONFIG_SYS_MALLOC_LEN)
  275. #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
  276. #define CONFIG_SPL_SERIAL_SUPPORT
  277. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  278. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  279. #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
  280. #define CONFIG_SPL_STACK 0x8001ff00
  281. #define CONFIG_SPL_TEXT_BASE 0x80000000
  282. #define CONFIG_SPL_MAX_SIZE 0x20000
  283. #define CONFIG_SPL_MAX_FOOTPRINT 32768
  284. /* additions for new relocation code, must added to all boards */
  285. #define CONFIG_SYS_SDRAM_BASE 0xc0000000
  286. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
  287. GENERATED_GBL_DATA_SIZE)
  288. /* add FALCON boot mode */
  289. #define CONFIG_CMD_SPL
  290. #define CONFIG_SPL_OS_BOOT
  291. #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
  292. #define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR
  293. #define CONFIG_CMD_SPL_NAND_OFS 0x00180000
  294. #define CONFIG_CMD_SPL_WRITE_SIZE 0x400
  295. /* GPIO support */
  296. #define CONFIG_SPL_GPIO_SUPPORT
  297. #define CONFIG_DA8XX_GPIO
  298. #define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14)
  299. #define CONFIG_SHOW_BOOT_PROGRESS
  300. #define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11)
  301. #define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12)
  302. #endif /* __CONFIG_H */