exynos5-dt.h 8.2 KB

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  1. /*
  2. * Copyright (C) 2013 Samsung Electronics
  3. *
  4. * Configuration settings for the SAMSUNG EXYNOS5 board.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. /* High Level Configuration Options */
  11. #define CONFIG_SAMSUNG /* in a SAMSUNG core */
  12. #define CONFIG_S5P /* S5P Family */
  13. #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
  14. #include <asm/arch/cpu.h> /* get chip and board defs */
  15. #define CONFIG_SYS_GENERIC_BOARD
  16. #define CONFIG_ARCH_CPU_INIT
  17. #define CONFIG_DISPLAY_CPUINFO
  18. #define CONFIG_DISPLAY_BOARDINFO
  19. #define CONFIG_BOARD_COMMON
  20. #define CONFIG_ARCH_EARLY_INIT_R
  21. #define CONFIG_EXYNOS_SPL
  22. /* Enable fdt support for Exynos5250 */
  23. #define CONFIG_OF_CONTROL
  24. #define CONFIG_OF_SEPARATE
  25. /* Allow tracing to be enabled */
  26. #define CONFIG_TRACE
  27. #define CONFIG_CMD_TRACE
  28. #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
  29. #define CONFIG_TRACE_EARLY_SIZE (8 << 20)
  30. #define CONFIG_TRACE_EARLY
  31. #define CONFIG_TRACE_EARLY_ADDR 0x50000000
  32. /* Keep L2 Cache Disabled */
  33. #define CONFIG_SYS_DCACHE_OFF
  34. #define CONFIG_SYS_CACHELINE_SIZE 64
  35. /* Enable ACE acceleration for SHA1 and SHA256 */
  36. #define CONFIG_EXYNOS_ACE_SHA
  37. #define CONFIG_SHA_HW_ACCEL
  38. /* input clock of PLL: SMDK5250 has 24MHz input clock */
  39. #define CONFIG_SYS_CLK_FREQ 24000000
  40. #define CONFIG_SETUP_MEMORY_TAGS
  41. #define CONFIG_CMDLINE_TAG
  42. #define CONFIG_INITRD_TAG
  43. #define CONFIG_CMDLINE_EDITING
  44. /* Power Down Modes */
  45. #define S5P_CHECK_SLEEP 0x00000BAD
  46. #define S5P_CHECK_DIDLE 0xBAD00000
  47. #define S5P_CHECK_LPA 0xABAD0000
  48. /* Offset for inform registers */
  49. #define INFORM0_OFFSET 0x800
  50. #define INFORM1_OFFSET 0x804
  51. #define INFORM2_OFFSET 0x808
  52. #define INFORM3_OFFSET 0x80c
  53. /* Size of malloc() pool */
  54. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
  55. /* select serial console configuration */
  56. #define CONFIG_BAUDRATE 115200
  57. #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
  58. #define CONFIG_SILENT_CONSOLE
  59. /* Enable keyboard */
  60. #define CONFIG_CROS_EC /* CROS_EC protocol */
  61. #define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
  62. #define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
  63. #define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
  64. #define CONFIG_CMD_CROS_EC
  65. #define CONFIG_KEYBOARD
  66. /* Console configuration */
  67. #define CONFIG_CONSOLE_MUX
  68. #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  69. #define EXYNOS_DEVICE_SETTINGS \
  70. "stdin=serial,cros-ec-keyb\0" \
  71. "stdout=serial,lcd\0" \
  72. "stderr=serial,lcd\0"
  73. #define CONFIG_EXTRA_ENV_SETTINGS \
  74. EXYNOS_DEVICE_SETTINGS
  75. /* SD/MMC configuration */
  76. #define CONFIG_GENERIC_MMC
  77. #define CONFIG_MMC
  78. #define CONFIG_SDHCI
  79. #define CONFIG_S5P_SDHCI
  80. #define CONFIG_DWMMC
  81. #define CONFIG_EXYNOS_DWMMC
  82. #define CONFIG_SUPPORT_EMMC_BOOT
  83. #define CONFIG_BOUNCE_BUFFER
  84. #define CONFIG_BOARD_EARLY_INIT_F
  85. #define CONFIG_SKIP_LOWLEVEL_INIT
  86. /* PWM */
  87. #define CONFIG_PWM
  88. /* allow to overwrite serial and ethaddr */
  89. #define CONFIG_ENV_OVERWRITE
  90. /* Command definition*/
  91. #include <config_cmd_default.h>
  92. #define CONFIG_CMD_PING
  93. #define CONFIG_CMD_ELF
  94. #define CONFIG_CMD_MMC
  95. #define CONFIG_CMD_EXT2
  96. #define CONFIG_CMD_FAT
  97. #define CONFIG_CMD_NET
  98. #define CONFIG_CMD_HASH
  99. #define CONFIG_BOOTDELAY 3
  100. #define CONFIG_ZERO_BOOTDELAY_CHECK
  101. /* Thermal Management Unit */
  102. #define CONFIG_EXYNOS_TMU
  103. #define CONFIG_CMD_DTT
  104. #define CONFIG_TMU_CMD_DTT
  105. /* TPM */
  106. #define CONFIG_TPM
  107. #define CONFIG_CMD_TPM
  108. #define CONFIG_TPM_TIS_I2C
  109. #define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
  110. #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
  111. /* MMC SPL */
  112. #define CONFIG_SPL 1
  113. #define COPY_BL2_FNPTR_ADDR 0x02020030
  114. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  115. #define CONFIG_SPL_GPIO_SUPPORT
  116. /* specific .lds file */
  117. #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
  118. /* Miscellaneous configurable options */
  119. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  120. #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  121. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  122. #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
  123. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  124. #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
  125. /* Boot Argument Buffer Size */
  126. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  127. /* memtest works on */
  128. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  129. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
  130. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
  131. #define CONFIG_RD_LVL
  132. #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
  133. #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
  134. #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
  135. #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
  136. #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
  137. #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
  138. #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
  139. #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
  140. #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
  141. #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
  142. #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
  143. #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
  144. #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
  145. #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
  146. #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
  147. #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
  148. #define CONFIG_SYS_MONITOR_BASE 0x00000000
  149. /* FLASH and environment organization */
  150. #define CONFIG_SYS_NO_FLASH
  151. #undef CONFIG_CMD_IMLS
  152. #define CONFIG_SYS_MMC_ENV_DEV 0
  153. #define CONFIG_SECURE_BL1_ONLY
  154. /* Secure FW size configuration */
  155. #ifdef CONFIG_SECURE_BL1_ONLY
  156. #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
  157. #else
  158. #define CONFIG_SEC_FW_SIZE 0
  159. #endif
  160. /* Configuration of BL1, BL2, ENV Blocks on mmc */
  161. #define CONFIG_RES_BLOCK_SIZE (512)
  162. #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
  163. #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
  164. #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
  165. #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
  166. #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
  167. /* Store environment at the end of a 4 MB SPI flash */
  168. #define FLASH_SIZE (0x4 << 20)
  169. #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
  170. /* U-boot copy size from boot Media to DRAM.*/
  171. #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
  172. #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
  173. #define CONFIG_SPI_BOOTING
  174. #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
  175. #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
  176. #define CONFIG_DOS_PARTITION
  177. #define CONFIG_EFI_PARTITION
  178. #define CONFIG_CMD_PART
  179. #define CONFIG_PARTITION_UUIDS
  180. /* I2C */
  181. #define CONFIG_SYS_I2C_INIT_BOARD
  182. #define CONFIG_SYS_I2C
  183. #define CONFIG_CMD_I2C
  184. #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
  185. #define CONFIG_SYS_I2C_S3C24X0
  186. #define CONFIG_I2C_MULTI_BUS
  187. #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
  188. #define CONFIG_I2C_EDID
  189. /* SPI */
  190. #define CONFIG_ENV_IS_IN_SPI_FLASH
  191. #define CONFIG_SPI_FLASH
  192. #define CONFIG_ENV_SPI_BASE 0x12D30000
  193. #ifdef CONFIG_SPI_FLASH
  194. #define CONFIG_EXYNOS_SPI
  195. #define CONFIG_CMD_SF
  196. #define CONFIG_CMD_SPI
  197. #define CONFIG_SPI_FLASH_WINBOND
  198. #define CONFIG_SPI_FLASH_GIGADEVICE
  199. #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  200. #define CONFIG_SF_DEFAULT_SPEED 50000000
  201. #define EXYNOS5_SPI_NUM_CONTROLLERS 5
  202. #define CONFIG_OF_SPI
  203. #endif
  204. #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  205. #define CONFIG_ENV_SPI_MODE SPI_MODE_0
  206. #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
  207. #define CONFIG_ENV_SPI_BUS 1
  208. #define CONFIG_ENV_SPI_MAX_HZ 50000000
  209. #endif
  210. /* PMIC */
  211. #define CONFIG_POWER
  212. #define CONFIG_POWER_I2C
  213. #define CONFIG_POWER_TPS65090
  214. /* Ethernet Controllor Driver */
  215. #ifdef CONFIG_CMD_NET
  216. #define CONFIG_SMC911X
  217. #define CONFIG_SMC911X_BASE 0x5000000
  218. #define CONFIG_SMC911X_16_BIT
  219. #define CONFIG_ENV_SROM_BANK 1
  220. #endif /*CONFIG_CMD_NET*/
  221. /* Enable PXE Support */
  222. #ifdef CONFIG_CMD_NET
  223. #define CONFIG_CMD_PXE
  224. #define CONFIG_MENU
  225. #endif
  226. /* Enable devicetree support */
  227. #define CONFIG_OF_LIBFDT
  228. /* SHA hashing */
  229. #define CONFIG_CMD_HASH
  230. #define CONFIG_HASH_VERIFY
  231. #define CONFIG_SHA1
  232. #define CONFIG_SHA256
  233. /* Enable Time Command */
  234. #define CONFIG_CMD_TIME
  235. #define CONFIG_CMD_BOOTZ
  236. #define CONFIG_CMD_GPIO
  237. /* USB boot mode */
  238. #define CONFIG_USB_BOOTING
  239. #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
  240. #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
  241. #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
  242. #endif /* __CONFIG_H */