devkit8000.h 11 KB

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  1. /*
  2. * (C) Copyright 2006-2008
  3. * Texas Instruments.
  4. * Richard Woodruff <r-woodruff2@ti.com>
  5. * Syed Mohammed Khasim <x0khasim@ti.com>
  6. *
  7. * (C) Copyright 2009
  8. * Frederik Kriewitz <frederik@kriewitz.eu>
  9. *
  10. * Configuration settings for the DevKit8000 board.
  11. *
  12. * SPDX-License-Identifier: GPL-2.0+
  13. */
  14. #ifndef __CONFIG_H
  15. #define __CONFIG_H
  16. /* High Level Configuration Options */
  17. #define CONFIG_OMAP 1 /* in a TI OMAP core */
  18. #define CONFIG_OMAP34XX 1 /* which is a 34XX */
  19. #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
  20. #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
  21. #define CONFIG_OMAP_GPIO
  22. #define CONFIG_OMAP_COMMON
  23. /*
  24. * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  25. * 64 bytes before this address should be set aside for u-boot.img's
  26. * header. That is 0x800FFFC0--0x80100000 should not be used for any
  27. * other needs.
  28. */
  29. #define CONFIG_SYS_TEXT_BASE 0x80100000
  30. #define CONFIG_SDRC /* The chip has SDRC controller */
  31. #include <asm/arch/cpu.h> /* get chip and board defs */
  32. #include <asm/arch/omap3.h>
  33. /* Display CPU and Board information */
  34. #define CONFIG_DISPLAY_CPUINFO 1
  35. #define CONFIG_DISPLAY_BOARDINFO 1
  36. /* Clock Defines */
  37. #define V_OSCK 26000000 /* Clock output from T2 */
  38. #define V_SCLK (V_OSCK >> 1)
  39. #define CONFIG_MISC_INIT_R
  40. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  41. #define CONFIG_SETUP_MEMORY_TAGS 1
  42. #define CONFIG_INITRD_TAG 1
  43. #define CONFIG_REVISION_TAG 1
  44. #define CONFIG_OF_LIBFDT 1
  45. /* Size of malloc() pool */
  46. #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
  47. /* Sector */
  48. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  49. /* Hardware drivers */
  50. /* DM9000 */
  51. #define CONFIG_NET_RETRY_COUNT 20
  52. #define CONFIG_DRIVER_DM9000 1
  53. #define CONFIG_DM9000_BASE 0x2c000000
  54. #define DM9000_IO CONFIG_DM9000_BASE
  55. #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
  56. #define CONFIG_DM9000_USE_16BIT 1
  57. #define CONFIG_DM9000_NO_SROM 1
  58. #undef CONFIG_DM9000_DEBUG
  59. /* NS16550 Configuration */
  60. #define CONFIG_SYS_NS16550
  61. #define CONFIG_SYS_NS16550_SERIAL
  62. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  63. #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  64. /* select serial console configuration */
  65. #define CONFIG_CONS_INDEX 3
  66. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  67. #define CONFIG_SERIAL3 3
  68. #define CONFIG_BAUDRATE 115200
  69. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  70. 115200}
  71. /* MMC */
  72. #define CONFIG_GENERIC_MMC 1
  73. #define CONFIG_MMC 1
  74. #define CONFIG_OMAP_HSMMC 1
  75. #define CONFIG_DOS_PARTITION 1
  76. /* I2C */
  77. #define CONFIG_SYS_I2C
  78. #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
  79. #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
  80. #define CONFIG_SYS_I2C_OMAP34XX
  81. /* TWL4030 */
  82. #define CONFIG_TWL4030_POWER 1
  83. #define CONFIG_TWL4030_LED 1
  84. /* Board NAND Info */
  85. #define CONFIG_SYS_NO_FLASH /* no NOR flash */
  86. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  87. #define MTDIDS_DEFAULT "nand0=nand"
  88. #define MTDPARTS_DEFAULT "mtdparts=nand:" \
  89. "512k(x-loader)," \
  90. "1920k(u-boot)," \
  91. "128k(u-boot-env)," \
  92. "4m(kernel)," \
  93. "-(fs)"
  94. #define CONFIG_NAND_OMAP_GPMC
  95. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  96. /* to access nand */
  97. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  98. /* to access nand at */
  99. /* CS0 */
  100. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  101. /* devices */
  102. #define CONFIG_JFFS2_NAND
  103. /* nand device jffs2 lives on */
  104. #define CONFIG_JFFS2_DEV "nand0"
  105. /* start of jffs2 partition */
  106. #define CONFIG_JFFS2_PART_OFFSET 0x680000
  107. #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
  108. /* partition */
  109. /* commands to include */
  110. #include <config_cmd_default.h>
  111. #define CONFIG_CMD_DHCP /* DHCP support */
  112. #define CONFIG_CMD_EXT2 /* EXT2 Support */
  113. #define CONFIG_CMD_FAT /* FAT support */
  114. #define CONFIG_CMD_I2C /* I2C serial bus support */
  115. #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
  116. #define CONFIG_CMD_MMC /* MMC support */
  117. #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
  118. #define CONFIG_CMD_NAND /* NAND support */
  119. #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
  120. #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
  121. #undef CONFIG_CMD_IMI /* iminfo */
  122. /* BOOTP/DHCP options */
  123. #define CONFIG_BOOTP_SUBNETMASK
  124. #define CONFIG_BOOTP_GATEWAY
  125. #define CONFIG_BOOTP_HOSTNAME
  126. #define CONFIG_BOOTP_NISDOMAIN
  127. #define CONFIG_BOOTP_BOOTPATH
  128. #define CONFIG_BOOTP_BOOTFILESIZE
  129. #define CONFIG_BOOTP_DNS
  130. #define CONFIG_BOOTP_DNS2
  131. #define CONFIG_BOOTP_SEND_HOSTNAME
  132. #define CONFIG_BOOTP_NTPSERVER
  133. #define CONFIG_BOOTP_TIMEOFFSET
  134. #undef CONFIG_BOOTP_VENDOREX
  135. /* Environment information */
  136. #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
  137. #define CONFIG_BOOTDELAY 3
  138. #define CONFIG_EXTRA_ENV_SETTINGS \
  139. "loadaddr=0x82000000\0" \
  140. "console=ttyO2,115200n8\0" \
  141. "mmcdev=0\0" \
  142. "vram=12M\0" \
  143. "dvimode=1024x768MR-16@60\0" \
  144. "defaultdisplay=dvi\0" \
  145. "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
  146. "kernelopts=rw\0" \
  147. "commonargs=" \
  148. "setenv bootargs console=${console} " \
  149. "vram=${vram} " \
  150. "omapfb.mode=dvi:${dvimode} " \
  151. "omapdss.def_disp=${defaultdisplay}\0" \
  152. "mmcargs=" \
  153. "run commonargs; " \
  154. "setenv bootargs ${bootargs} " \
  155. "root=/dev/mmcblk0p2 " \
  156. "rootwait " \
  157. "${kernelopts}\0" \
  158. "nandargs=" \
  159. "run commonargs; " \
  160. "setenv bootargs ${bootargs} " \
  161. "omapfb.mode=dvi:${dvimode} " \
  162. "omapdss.def_disp=${defaultdisplay} " \
  163. "root=/dev/mtdblock4 " \
  164. "rootfstype=jffs2 " \
  165. "${kernelopts}\0" \
  166. "netargs=" \
  167. "run commonargs; " \
  168. "setenv bootargs ${bootargs} " \
  169. "root=/dev/nfs " \
  170. "nfsroot=${serverip}:${rootpath},${nfsopts} " \
  171. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
  172. "${kernelopts} " \
  173. "dnsip1=${dnsip} " \
  174. "dnsip2=${dnsip2}\0" \
  175. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  176. "bootscript=echo Running bootscript from mmc ...; " \
  177. "source ${loadaddr}\0" \
  178. "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  179. "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
  180. "mmcboot=echo Booting from mmc ...; " \
  181. "run mmcargs; " \
  182. "bootm ${loadaddr}\0" \
  183. "nandboot=echo Booting from nand ...; " \
  184. "run nandargs; " \
  185. "nand read ${loadaddr} 280000 400000; " \
  186. "bootm ${loadaddr}\0" \
  187. "netboot=echo Booting from network ...; " \
  188. "dhcp ${loadaddr}; " \
  189. "run netargs; " \
  190. "bootm ${loadaddr}\0" \
  191. "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
  192. "if run loadbootscript; then " \
  193. "run bootscript; " \
  194. "else " \
  195. "if run loaduimage; then " \
  196. "run mmcboot; " \
  197. "else run nandboot; " \
  198. "fi; " \
  199. "fi; " \
  200. "else run nandboot; fi\0"
  201. #define CONFIG_BOOTCOMMAND "run autoboot"
  202. /* Miscellaneous configurable options */
  203. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  204. #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  205. #define CONFIG_AUTO_COMPLETE 1
  206. #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
  207. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  208. /* Print Buffer Size */
  209. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  210. sizeof(CONFIG_SYS_PROMPT) + 16)
  211. #define CONFIG_SYS_MAXARGS 128 /* max number of command args */
  212. /* Boot Argument Buffer Size */
  213. #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  214. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
  215. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
  216. 0x01000000) /* 16MB */
  217. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
  218. /*
  219. * OMAP3 has 12 GP timers, they can be driven by the system clock
  220. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  221. * This rate is divided by a local divisor.
  222. */
  223. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  224. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  225. /* Physical Memory Map */
  226. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  227. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  228. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  229. /* NAND and environment organization */
  230. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  231. #define CONFIG_ENV_IS_IN_NAND 1
  232. #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
  233. #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
  234. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  235. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  236. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  237. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  238. CONFIG_SYS_INIT_RAM_SIZE - \
  239. GENERATED_GBL_DATA_SIZE)
  240. /* SRAM config */
  241. #define CONFIG_SYS_SRAM_START 0x40200000
  242. #define CONFIG_SYS_SRAM_SIZE 0x10000
  243. /* Defines for SPL */
  244. #define CONFIG_SPL 1
  245. #define CONFIG_SPL_FRAMEWORK
  246. #define CONFIG_SPL_NAND_SIMPLE
  247. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  248. #define CONFIG_SPL_LIBDISK_SUPPORT
  249. #define CONFIG_SPL_BOARD_INIT
  250. #define CONFIG_SPL_I2C_SUPPORT
  251. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  252. #define CONFIG_SPL_SERIAL_SUPPORT
  253. #define CONFIG_SPL_GPIO_SUPPORT
  254. #define CONFIG_SPL_POWER_SUPPORT
  255. #define CONFIG_SPL_NAND_SUPPORT
  256. #define CONFIG_SPL_NAND_BASE
  257. #define CONFIG_SPL_NAND_DRIVERS
  258. #define CONFIG_SPL_NAND_ECC
  259. #define CONFIG_SPL_MMC_SUPPORT
  260. #define CONFIG_SPL_FAT_SUPPORT
  261. #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
  262. #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
  263. #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
  264. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
  265. #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
  266. #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
  267. #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
  268. #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
  269. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  270. /* NAND boot config */
  271. #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
  272. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  273. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  274. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  275. #define CONFIG_SYS_NAND_OOBSIZE 64
  276. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  277. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  278. #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
  279. 10, 11, 12, 13}
  280. #define CONFIG_SYS_NAND_ECCSIZE 512
  281. #define CONFIG_SYS_NAND_ECCBYTES 3
  282. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
  283. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  284. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  285. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
  286. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  287. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
  288. /* SPL OS boot options */
  289. #define CONFIG_SPL_OS_BOOT
  290. #define CONFIG_CMD_SPL
  291. #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
  292. #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
  293. 0x400000)
  294. #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
  295. #define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
  296. #define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args"
  297. #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
  298. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
  299. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
  300. #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
  301. #endif /* __CONFIG_H */