cm_t35.h 11 KB

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  1. /*
  2. * (C) Copyright 2011 CompuLab, Ltd.
  3. * Mike Rapoport <mike@compulab.co.il>
  4. * Igor Grinberg <grinberg@compulab.co.il>
  5. *
  6. * Based on omap3_beagle.h
  7. * (C) Copyright 2006-2008
  8. * Texas Instruments.
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. * Syed Mohammed Khasim <x0khasim@ti.com>
  11. *
  12. * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
  13. *
  14. * SPDX-License-Identifier: GPL-2.0+
  15. */
  16. #ifndef __CONFIG_H
  17. #define __CONFIG_H
  18. /*
  19. * High Level Configuration Options
  20. */
  21. #define CONFIG_OMAP /* in a TI OMAP core */
  22. #define CONFIG_OMAP34XX /* which is a 34XX */
  23. #define CONFIG_OMAP_GPIO
  24. #define CONFIG_CMD_GPIO
  25. #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
  26. #define CONFIG_OMAP_COMMON
  27. #define CONFIG_SDRC /* The chip has SDRC controller */
  28. #include <asm/arch/cpu.h> /* get chip and board defs */
  29. #include <asm/arch/omap3.h>
  30. /*
  31. * Display CPU and Board information
  32. */
  33. #define CONFIG_DISPLAY_CPUINFO
  34. #define CONFIG_DISPLAY_BOARDINFO
  35. /* Clock Defines */
  36. #define V_OSCK 26000000 /* Clock output from T2 */
  37. #define V_SCLK (V_OSCK >> 1)
  38. #define CONFIG_MISC_INIT_R
  39. #define CONFIG_OF_LIBFDT 1
  40. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  41. #define CONFIG_SETUP_MEMORY_TAGS
  42. #define CONFIG_INITRD_TAG
  43. #define CONFIG_REVISION_TAG
  44. #define CONFIG_SERIAL_TAG
  45. /*
  46. * Size of malloc() pool
  47. */
  48. #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
  49. /* Sector */
  50. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  51. /*
  52. * Hardware drivers
  53. */
  54. /*
  55. * NS16550 Configuration
  56. */
  57. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  58. #define CONFIG_SYS_NS16550
  59. #define CONFIG_SYS_NS16550_SERIAL
  60. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  61. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  62. /*
  63. * select serial console configuration
  64. */
  65. #define CONFIG_CONS_INDEX 3
  66. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  67. #define CONFIG_SERIAL3 3 /* UART3 */
  68. /* allow to overwrite serial and ethaddr */
  69. #define CONFIG_ENV_OVERWRITE
  70. #define CONFIG_BAUDRATE 115200
  71. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  72. 115200}
  73. #define CONFIG_GENERIC_MMC
  74. #define CONFIG_MMC
  75. #define CONFIG_OMAP_HSMMC
  76. #define CONFIG_DOS_PARTITION
  77. /* USB */
  78. #define CONFIG_USB_OMAP3
  79. #define CONFIG_USB_EHCI
  80. #define CONFIG_USB_EHCI_OMAP
  81. #define CONFIG_USB_STORAGE
  82. #define CONFIG_MUSB_UDC
  83. #define CONFIG_TWL4030_USB
  84. #define CONFIG_CMD_USB
  85. /* USB device configuration */
  86. #define CONFIG_USB_DEVICE
  87. #define CONFIG_USB_TTY
  88. #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  89. /* commands to include */
  90. #include <config_cmd_default.h>
  91. #define CONFIG_CMD_CACHE
  92. #define CONFIG_CMD_EXT2 /* EXT2 Support */
  93. #define CONFIG_CMD_FAT /* FAT support */
  94. #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
  95. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  96. #define CONFIG_MTD_PARTITIONS
  97. #define MTDIDS_DEFAULT "nand0=nand"
  98. #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
  99. "1920k(u-boot),256k(u-boot-env),"\
  100. "4m(kernel),-(fs)"
  101. #define CONFIG_CMD_I2C /* I2C serial bus support */
  102. #define CONFIG_CMD_MMC /* MMC support */
  103. #define CONFIG_CMD_NAND /* NAND support */
  104. #define CONFIG_CMD_DHCP
  105. #define CONFIG_CMD_PING
  106. #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
  107. #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
  108. #undef CONFIG_CMD_IMLS /* List all found images */
  109. #define CONFIG_SYS_NO_FLASH
  110. #define CONFIG_SYS_I2C
  111. #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
  112. #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
  113. #define CONFIG_SYS_I2C_OMAP34XX
  114. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  115. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  116. #define CONFIG_I2C_MULTI_BUS
  117. /*
  118. * TWL4030
  119. */
  120. #define CONFIG_TWL4030_POWER
  121. #define CONFIG_TWL4030_LED
  122. /*
  123. * Board NAND Info.
  124. */
  125. #define CONFIG_SYS_NAND_QUIET_TEST
  126. #define CONFIG_NAND_OMAP_GPMC
  127. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  128. /* to access nand */
  129. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  130. /* to access nand at */
  131. /* CS0 */
  132. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  133. /* devices */
  134. /* Environment information */
  135. #define CONFIG_BOOTDELAY 3
  136. #define CONFIG_ZERO_BOOTDELAY_CHECK
  137. #define CONFIG_EXTRA_ENV_SETTINGS \
  138. "loadaddr=0x82000000\0" \
  139. "usbtty=cdc_acm\0" \
  140. "console=ttyO2,115200n8\0" \
  141. "mpurate=500\0" \
  142. "vram=12M\0" \
  143. "dvimode=1024x768MR-16@60\0" \
  144. "defaultdisplay=dvi\0" \
  145. "mmcdev=0\0" \
  146. "mmcroot=/dev/mmcblk0p2 rw\0" \
  147. "mmcrootfstype=ext4 rootwait\0" \
  148. "nandroot=/dev/mtdblock4 rw\0" \
  149. "nandrootfstype=ubifs\0" \
  150. "mmcargs=setenv bootargs console=${console} " \
  151. "mpurate=${mpurate} " \
  152. "vram=${vram} " \
  153. "omapfb.mode=dvi:${dvimode} " \
  154. "omapdss.def_disp=${defaultdisplay} " \
  155. "root=${mmcroot} " \
  156. "rootfstype=${mmcrootfstype}\0" \
  157. "nandargs=setenv bootargs console=${console} " \
  158. "mpurate=${mpurate} " \
  159. "vram=${vram} " \
  160. "omapfb.mode=dvi:${dvimode} " \
  161. "omapdss.def_disp=${defaultdisplay} " \
  162. "root=${nandroot} " \
  163. "rootfstype=${nandrootfstype}\0" \
  164. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  165. "bootscript=echo Running bootscript from mmc ...; " \
  166. "source ${loadaddr}\0" \
  167. "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  168. "mmcboot=echo Booting from mmc ...; " \
  169. "run mmcargs; " \
  170. "bootm ${loadaddr}\0" \
  171. "nandboot=echo Booting from nand ...; " \
  172. "run nandargs; " \
  173. "nand read ${loadaddr} 2a0000 400000; " \
  174. "bootm ${loadaddr}\0" \
  175. #define CONFIG_CMD_BOOTZ
  176. #define CONFIG_BOOTCOMMAND \
  177. "mmc dev ${mmcdev}; if mmc rescan; then " \
  178. "if run loadbootscript; then " \
  179. "run bootscript; " \
  180. "else " \
  181. "if run loaduimage; then " \
  182. "run mmcboot; " \
  183. "else run nandboot; " \
  184. "fi; " \
  185. "fi; " \
  186. "else run nandboot; fi"
  187. /*
  188. * Miscellaneous configurable options
  189. */
  190. #define CONFIG_AUTO_COMPLETE
  191. #define CONFIG_CMDLINE_EDITING
  192. #define CONFIG_TIMESTAMP
  193. #define CONFIG_SYS_AUTOLOAD "no"
  194. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  195. #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  196. #define CONFIG_SYS_PROMPT "CM-T3x # "
  197. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  198. /* Print Buffer Size */
  199. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  200. sizeof(CONFIG_SYS_PROMPT) + 16)
  201. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  202. /* Boot Argument Buffer Size */
  203. #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  204. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
  205. /* works on */
  206. #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
  207. 0x01F00000) /* 31MB */
  208. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
  209. /* load address */
  210. /*
  211. * OMAP3 has 12 GP timers, they can be driven by the system clock
  212. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  213. * This rate is divided by a local divisor.
  214. */
  215. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  216. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  217. /*-----------------------------------------------------------------------
  218. * Physical Memory Map
  219. */
  220. #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
  221. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  222. /*-----------------------------------------------------------------------
  223. * FLASH and environment organization
  224. */
  225. /* **** PISMO SUPPORT *** */
  226. /* Monitor at start of flash */
  227. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  228. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  229. #define CONFIG_ENV_IS_IN_NAND
  230. #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
  231. #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
  232. #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
  233. #if defined(CONFIG_CMD_NET)
  234. #define CONFIG_SMC911X
  235. #define CONFIG_SMC911X_32_BIT
  236. #define CM_T3X_SMC911X_BASE 0x2C000000
  237. #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
  238. #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
  239. #endif /* (CONFIG_CMD_NET) */
  240. /* additions for new relocation code, must be added to all boards */
  241. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  242. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  243. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  244. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  245. CONFIG_SYS_INIT_RAM_SIZE - \
  246. GENERATED_GBL_DATA_SIZE)
  247. /* Status LED */
  248. #define CONFIG_STATUS_LED /* Status LED enabled */
  249. #define CONFIG_BOARD_SPECIFIC_LED
  250. #define CONFIG_GPIO_LED
  251. #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
  252. #define GREEN_LED_DEV 0
  253. #define STATUS_LED_BIT GREEN_LED_GPIO
  254. #define STATUS_LED_STATE STATUS_LED_ON
  255. #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
  256. #define STATUS_LED_BOOT GREEN_LED_DEV
  257. #define CONFIG_SPLASHIMAGE_GUARD
  258. /* GPIO banks */
  259. #ifdef CONFIG_STATUS_LED
  260. #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
  261. #endif
  262. /* Display Configuration */
  263. #define CONFIG_OMAP3_GPIO_2
  264. #define CONFIG_OMAP3_GPIO_5
  265. #define CONFIG_VIDEO_OMAP3
  266. #define LCD_BPP LCD_COLOR16
  267. #define CONFIG_LCD
  268. #define CONFIG_SPLASH_SCREEN
  269. #define CONFIG_CMD_BMP
  270. #define CONFIG_BMP_16BPP
  271. #define CONFIG_SCF0403_LCD
  272. #define CONFIG_OMAP3_SPI
  273. /* Defines for SPL */
  274. #define CONFIG_SPL 1
  275. #define CONFIG_SPL_FRAMEWORK
  276. #define CONFIG_SPL_NAND_SIMPLE
  277. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
  278. #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
  279. #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
  280. #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
  281. #define CONFIG_SPL_BOARD_INIT
  282. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  283. #define CONFIG_SPL_LIBDISK_SUPPORT
  284. #define CONFIG_SPL_I2C_SUPPORT
  285. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  286. #define CONFIG_SPL_MMC_SUPPORT
  287. #define CONFIG_SPL_FAT_SUPPORT
  288. #define CONFIG_SPL_SERIAL_SUPPORT
  289. #define CONFIG_SPL_NAND_SUPPORT
  290. #define CONFIG_SPL_NAND_BASE
  291. #define CONFIG_SPL_NAND_DRIVERS
  292. #define CONFIG_SPL_NAND_ECC
  293. #define CONFIG_SPL_GPIO_SUPPORT
  294. #define CONFIG_SPL_POWER_SUPPORT
  295. #define CONFIG_SPL_OMAP3_ID_NAND
  296. #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
  297. /* NAND boot config */
  298. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  299. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  300. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  301. #define CONFIG_SYS_NAND_OOBSIZE 64
  302. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  303. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  304. /*
  305. * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
  306. * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
  307. */
  308. #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
  309. 10, 11, 12 }
  310. #define CONFIG_SYS_NAND_ECCSIZE 512
  311. #define CONFIG_SYS_NAND_ECCBYTES 3
  312. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
  313. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  314. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  315. #define CONFIG_SPL_TEXT_BASE 0x40200800
  316. #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
  317. #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
  318. /*
  319. * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
  320. * older x-loader implementations. And move the BSS area so that it
  321. * doesn't overlap with TEXT_BASE.
  322. */
  323. #define CONFIG_SYS_TEXT_BASE 0x80008000
  324. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  325. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
  326. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  327. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  328. #endif /* __CONFIG_H */