am3517_crane.h 10 KB

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  1. /*
  2. * am3517_crane.h - Default configuration for AM3517 CraneBoard.
  3. *
  4. * Author: Srinath.R <srinath@mistralsolutions.com>
  5. *
  6. * Based on include/configs/am3517evm.h
  7. *
  8. * Copyright (C) 2011 Mistral Solutions pvt Ltd
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. /*
  15. * High Level Configuration Options
  16. */
  17. #define CONFIG_OMAP 1 /* in a TI OMAP core */
  18. #define CONFIG_OMAP34XX 1 /* which is a 34XX */
  19. #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
  20. #define CONFIG_OMAP_COMMON
  21. #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
  22. #include <asm/arch/cpu.h> /* get chip and board defs */
  23. #include <asm/arch/omap3.h>
  24. /*
  25. * Display CPU and Board information
  26. */
  27. #define CONFIG_DISPLAY_CPUINFO 1
  28. #define CONFIG_DISPLAY_BOARDINFO 1
  29. /* Clock Defines */
  30. #define V_OSCK 26000000 /* Clock output from T2 */
  31. #define V_SCLK (V_OSCK >> 1)
  32. #define CONFIG_MISC_INIT_R
  33. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  34. #define CONFIG_SETUP_MEMORY_TAGS 1
  35. #define CONFIG_INITRD_TAG 1
  36. #define CONFIG_REVISION_TAG 1
  37. /*
  38. * Size of malloc() pool
  39. */
  40. #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
  41. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  42. /* initial data */
  43. /*
  44. * DDR related
  45. */
  46. #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
  47. /*
  48. * Hardware drivers
  49. */
  50. /*
  51. * NS16550 Configuration
  52. */
  53. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  54. #define CONFIG_SYS_NS16550
  55. #define CONFIG_SYS_NS16550_SERIAL
  56. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  57. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  58. /*
  59. * select serial console configuration
  60. */
  61. #define CONFIG_CONS_INDEX 3
  62. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  63. #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
  64. /* allow to overwrite serial and ethaddr */
  65. #define CONFIG_ENV_OVERWRITE
  66. #define CONFIG_BAUDRATE 115200
  67. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  68. 115200}
  69. #define CONFIG_GENERIC_MMC 1
  70. #define CONFIG_MMC 1
  71. #define CONFIG_OMAP_HSMMC 1
  72. #define CONFIG_DOS_PARTITION 1
  73. /*
  74. * USB configuration
  75. * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
  76. * Enable CONFIG_MUSB_UDC for Device functionalities.
  77. */
  78. #define CONFIG_USB_AM35X 1
  79. #define CONFIG_MUSB_HCD 1
  80. #ifdef CONFIG_USB_AM35X
  81. #ifdef CONFIG_MUSB_HCD
  82. #define CONFIG_CMD_USB
  83. #define CONFIG_USB_STORAGE
  84. #define CONGIG_CMD_STORAGE
  85. #define CONFIG_CMD_FAT
  86. #ifdef CONFIG_USB_KEYBOARD
  87. #define CONFIG_SYS_USB_EVENT_POLL
  88. #define CONFIG_PREBOOT "usb start"
  89. #endif /* CONFIG_USB_KEYBOARD */
  90. #endif /* CONFIG_MUSB_HCD */
  91. #ifdef CONFIG_MUSB_UDC
  92. /* USB device configuration */
  93. #define CONFIG_USB_DEVICE 1
  94. #define CONFIG_USB_TTY 1
  95. #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
  96. /* Change these to suit your needs */
  97. #define CONFIG_USBD_VENDORID 0x0451
  98. #define CONFIG_USBD_PRODUCTID 0x5678
  99. #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
  100. #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
  101. #endif /* CONFIG_MUSB_UDC */
  102. #endif /* CONFIG_USB_AM35X */
  103. /* commands to include */
  104. #include <config_cmd_default.h>
  105. #define CONFIG_CMD_EXT2 /* EXT2 Support */
  106. #define CONFIG_CMD_FAT /* FAT support */
  107. #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
  108. #define CONFIG_CMD_I2C /* I2C serial bus support */
  109. #define CONFIG_CMD_MMC /* MMC support */
  110. #define CONFIG_CMD_NAND /* NAND support */
  111. #define CONFIG_CMD_DHCP
  112. #undef CONFIG_CMD_PING
  113. #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
  114. #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
  115. #undef CONFIG_CMD_IMI /* iminfo */
  116. #undef CONFIG_CMD_IMLS /* List all found images */
  117. #define CONFIG_SYS_NO_FLASH
  118. #define CONFIG_SYS_I2C
  119. #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
  120. #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
  121. #define CONFIG_SYS_I2C_OMAP34XX
  122. #undef CONFIG_CMD_NET
  123. #undef CONFIG_CMD_NFS
  124. /*
  125. * Board NAND Info.
  126. */
  127. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  128. /* to access nand */
  129. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  130. /* to access */
  131. /* nand at CS0 */
  132. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
  133. /* NAND devices */
  134. #define CONFIG_JFFS2_NAND
  135. /* nand device jffs2 lives on */
  136. #define CONFIG_JFFS2_DEV "nand0"
  137. /* start of jffs2 partition */
  138. #define CONFIG_JFFS2_PART_OFFSET 0x680000
  139. #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
  140. /* Environment information */
  141. #define CONFIG_BOOTDELAY 10
  142. #define CONFIG_BOOTFILE "uImage"
  143. #define CONFIG_EXTRA_ENV_SETTINGS \
  144. "loadaddr=0x82000000\0" \
  145. "console=ttyS2,115200n8\0" \
  146. "mmcdev=0\0" \
  147. "mmcargs=setenv bootargs console=${console} " \
  148. "root=/dev/mmcblk0p2 rw " \
  149. "rootfstype=ext3 rootwait\0" \
  150. "nandargs=setenv bootargs console=${console} " \
  151. "root=/dev/mtdblock4 rw " \
  152. "rootfstype=jffs2\0" \
  153. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  154. "bootscript=echo Running bootscript from mmc ...; " \
  155. "source ${loadaddr}\0" \
  156. "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  157. "mmcboot=echo Booting from mmc ...; " \
  158. "run mmcargs; " \
  159. "bootm ${loadaddr}\0" \
  160. "nandboot=echo Booting from nand ...; " \
  161. "run nandargs; " \
  162. "nand read ${loadaddr} 280000 400000; " \
  163. "bootm ${loadaddr}\0" \
  164. #define CONFIG_BOOTCOMMAND \
  165. "mmc dev ${mmcdev}; if mmc rescan; then " \
  166. "if run loadbootscript; then " \
  167. "run bootscript; " \
  168. "else " \
  169. "if run loaduimage; then " \
  170. "run mmcboot; " \
  171. "else run nandboot; " \
  172. "fi; " \
  173. "fi; " \
  174. "else run nandboot; fi"
  175. #define CONFIG_AUTO_COMPLETE 1
  176. /*
  177. * Miscellaneous configurable options
  178. */
  179. #define V_PROMPT "AM3517_CRANE # "
  180. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  181. #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  182. #define CONFIG_SYS_PROMPT V_PROMPT
  183. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  184. /* Print Buffer Size */
  185. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  186. sizeof(CONFIG_SYS_PROMPT) + 16)
  187. #define CONFIG_SYS_MAXARGS 32 /* max number of command */
  188. /* args */
  189. /* Boot Argument Buffer Size */
  190. #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  191. /* memtest works on */
  192. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
  193. #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
  194. 0x01F00000) /* 31MB */
  195. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
  196. /* address */
  197. /*
  198. * AM3517 has 12 GP timers, they can be driven by the system clock
  199. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  200. * This rate is divided by a local divisor.
  201. */
  202. #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
  203. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  204. /*-----------------------------------------------------------------------
  205. * Physical Memory Map
  206. */
  207. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  208. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  209. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  210. /*-----------------------------------------------------------------------
  211. * FLASH and environment organization
  212. */
  213. /* **** PISMO SUPPORT *** */
  214. #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
  215. /* on one chip */
  216. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
  217. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  218. #define CONFIG_SYS_FLASH_BASE NAND_BASE
  219. /* Monitor at start of flash */
  220. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  221. #define CONFIG_NAND_OMAP_GPMC
  222. #define CONFIG_ENV_IS_IN_NAND 1
  223. #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
  224. #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
  225. #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
  226. #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
  227. /*-----------------------------------------------------------------------
  228. * CFI FLASH driver setup
  229. */
  230. /* timeout values are in ticks */
  231. #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
  232. #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
  233. /* Flash banks JFFS2 should use */
  234. #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
  235. CONFIG_SYS_MAX_NAND_DEVICE)
  236. #define CONFIG_SYS_JFFS2_MEM_NAND
  237. /* use flash_info[2] */
  238. #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
  239. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  240. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  241. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  242. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  243. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  244. CONFIG_SYS_INIT_RAM_SIZE - \
  245. GENERATED_GBL_DATA_SIZE)
  246. /* Defines for SPL */
  247. #define CONFIG_SPL 1
  248. #define CONFIG_SPL_FRAMEWORK
  249. #define CONFIG_SPL_BOARD_INIT
  250. #define CONFIG_SPL_NAND_SIMPLE
  251. #define CONFIG_SPL_TEXT_BASE 0x40200800
  252. #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
  253. #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
  254. #define CONFIG_SPL_BSS_START_ADDR 0x80000000
  255. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
  256. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
  257. #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
  258. #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
  259. #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
  260. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  261. #define CONFIG_SPL_LIBDISK_SUPPORT
  262. #define CONFIG_SPL_I2C_SUPPORT
  263. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  264. #define CONFIG_SPL_MMC_SUPPORT
  265. #define CONFIG_SPL_FAT_SUPPORT
  266. #define CONFIG_SPL_SERIAL_SUPPORT
  267. #define CONFIG_SPL_NAND_SUPPORT
  268. #define CONFIG_SPL_NAND_BASE
  269. #define CONFIG_SPL_NAND_DRIVERS
  270. #define CONFIG_SPL_NAND_ECC
  271. #define CONFIG_SPL_POWER_SUPPORT
  272. #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
  273. /* NAND boot config */
  274. #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
  275. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  276. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  277. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  278. #define CONFIG_SYS_NAND_OOBSIZE 64
  279. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  280. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  281. #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
  282. 10, 11, 12, 13}
  283. #define CONFIG_SYS_NAND_ECCSIZE 512
  284. #define CONFIG_SYS_NAND_ECCBYTES 3
  285. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
  286. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  287. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  288. /*
  289. * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  290. * 64 bytes before this address should be set aside for u-boot.img's
  291. * header. That is 0x800FFFC0--0x80100000 should not be used for any
  292. * other needs.
  293. */
  294. #define CONFIG_SYS_TEXT_BASE 0x80100000
  295. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  296. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  297. #endif /* __CONFIG_H */