a3m071.h 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443
  1. /*
  2. * Copyright 2012-2013 Stefan Roese <sr@denx.de>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. /*
  9. * High Level Configuration Options
  10. * (easy to change)
  11. */
  12. #define CONFIG_MPC5200
  13. #define CONFIG_A3M071 /* A3M071 board */
  14. #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
  15. #define CONFIG_SPL_TARGET "u-boot-img.bin"
  16. #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
  17. #define CONFIG_MISC_INIT_R
  18. #define CONFIG_SYS_LOWBOOT /* Enable lowboot */
  19. #ifdef CONFIG_A4M2K
  20. #define CONFIG_HOSTNAME a4m2k
  21. #else
  22. #define CONFIG_HOSTNAME a3m071
  23. #endif
  24. #define CONFIG_BOOTCOUNT_LIMIT
  25. /*
  26. * Serial console configuration
  27. */
  28. #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
  29. #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
  30. #define CONFIG_SYS_BAUDRATE_TABLE \
  31. { 9600, 19200, 38400, 57600, 115200, 230400 }
  32. /*
  33. * Command line configuration.
  34. */
  35. #include <config_cmd_default.h>
  36. #define CONFIG_CMD_BSP
  37. #define CONFIG_CMD_CACHE
  38. #define CONFIG_CMD_MII
  39. #define CONFIG_CMD_REGINFO
  40. #define CONFIG_CMD_DHCP
  41. #define CONFIG_BOOTP_SEND_HOSTNAME
  42. #define CONFIG_BOOTP_SERVERIP
  43. #define CONFIG_BOOTP_MAY_FAIL
  44. #define CONFIG_BOOTP_BOOTPATH
  45. #define CONFIG_BOOTP_GATEWAY
  46. #define CONFIG_BOOTP_SERVERIP
  47. #define CONFIG_NET_RETRY_COUNT 3
  48. #define CONFIG_CMD_LINK_LOCAL
  49. #define CONFIG_LIB_RAND
  50. #define CONFIG_NETCONSOLE
  51. #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  52. #define CONFIG_CMD_PING
  53. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  54. #define CONFIG_MTD_PARTITIONS /* needed for UBI */
  55. #define CONFIG_FLASH_CFI_MTD
  56. #define MTDIDS_DEFAULT "nor0=fc000000.flash"
  57. #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
  58. "128k(env1)," \
  59. "128k(env2)," \
  60. "128k(hwinfo)," \
  61. "1M(nvramsim)," \
  62. "128k(dtb)," \
  63. "5M(kernel)," \
  64. "128k(sysinfo)," \
  65. "7552k(root)," \
  66. "4M(app)," \
  67. "5376k(data)," \
  68. "8M(install)"
  69. #define CONFIG_LZO /* needed for UBI */
  70. #define CONFIG_RBTREE /* needed for UBI */
  71. #define CONFIG_CMD_MTDPARTS
  72. #define CONFIG_CMD_UBI
  73. #define CONFIG_CMD_UBIFS
  74. #define CONFIG_FIT
  75. /*
  76. * IPB Bus clocking configuration.
  77. */
  78. #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
  79. /* define for 66MHz speed - undef for 33MHz PCI clock speed */
  80. #ifdef CONFIG_A4M2K
  81. #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
  82. #else
  83. #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
  84. #endif
  85. /* pass open firmware flat tree */
  86. #define CONFIG_OF_LIBFDT
  87. #define CONFIG_OF_BOARD_SETUP
  88. /* maximum size of the flat tree (8K) */
  89. #define OF_FLAT_TREE_MAX_SIZE 8192
  90. #define OF_CPU "PowerPC,5200@0"
  91. #define OF_SOC "soc5200@f0000000"
  92. #define OF_TBCLK (bd->bi_busfreq / 4)
  93. #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
  94. /*
  95. * NOR flash configuration
  96. */
  97. #define CONFIG_SYS_FLASH_BASE 0xfc000000
  98. #define CONFIG_SYS_FLASH_SIZE 0x02000000
  99. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
  100. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  101. #define CONFIG_SYS_MAX_FLASH_SECT 256
  102. #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
  103. #define CONFIG_SYS_FLASH_WRITE_TOUT 500
  104. #define CONFIG_SYS_FLASH_LOCK_TOUT 5
  105. #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
  106. #define CONFIG_SYS_FLASH_PROTECTION
  107. #define CONFIG_FLASH_CFI_DRIVER
  108. #define CONFIG_SYS_FLASH_CFI
  109. #define CONFIG_SYS_FLASH_EMPTY_INFO
  110. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  111. #define CONFIG_FLASH_VERIFY
  112. /*
  113. * Environment settings
  114. */
  115. #define CONFIG_ENV_IS_IN_FLASH
  116. #define CONFIG_ENV_SIZE 0x10000
  117. #define CONFIG_ENV_SECT_SIZE 0x20000
  118. #define CONFIG_ENV_OVERWRITE
  119. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  120. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  121. /*
  122. * Memory map
  123. */
  124. #define CONFIG_SYS_MBAR 0xf0000000
  125. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  126. #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
  127. /* Use SRAM until RAM will be available */
  128. #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
  129. #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
  130. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
  131. GENERATED_GBL_DATA_SIZE)
  132. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  133. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  134. #define CONFIG_SYS_MONITOR_LEN (512 << 10)
  135. #define CONFIG_SYS_MALLOC_LEN (4 << 20)
  136. #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
  137. /*
  138. * Ethernet configuration
  139. */
  140. #define CONFIG_MPC5xxx_FEC
  141. #define CONFIG_MPC5xxx_FEC_MII100
  142. #ifdef CONFIG_A4M2K
  143. #define CONFIG_PHY_ADDR 0x01
  144. #else
  145. #define CONFIG_PHY_ADDR 0x00
  146. #endif
  147. /*
  148. * GPIO configuration
  149. */
  150. /*
  151. * GPIO-config depends on failsave-level
  152. * failsave 0 means just MPX-config, no digiboard, no fpga
  153. * 1 means digiboard ok
  154. * 2 means fpga ok
  155. */
  156. #ifdef CONFIG_A4M2K
  157. #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
  158. #else
  159. /* for failsave-level 0 - full failsave */
  160. #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
  161. /* for failsave-level 1 - only digiboard ok */
  162. #define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
  163. /* for failsave-level 2 - all ok */
  164. #define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
  165. #endif
  166. #define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
  167. #if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
  168. #define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
  169. #endif
  170. /*
  171. * Configuration matrix
  172. * MSB LSB
  173. * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
  174. * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
  175. * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
  176. * || ||| || | ||| | | | |
  177. * || ||| || | ||| | | | | bit rev name
  178. * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
  179. * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
  180. * ||| || | ||| | | | | 2 29 ALTs
  181. * +++-++--+---+++-+---+---+---+- 3 28 ALTs
  182. * ++-++--+---+++-+---+---+---+- 4 27 CS7
  183. * +-++--+---+++-+---+---+---+- 5 26 CS6
  184. * || | ||| | | | | 6 25 ATA
  185. * ++--+---+++-+---+---+---+- 7 24 ATA
  186. * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
  187. * | ||| | | | | 9 22 IRDA
  188. * | ||| | | | | 10 21 IRDA
  189. * +---+++-+---+---+---+- 11 20 IRDA
  190. * ||| | | | | 12 19 Ether
  191. * ||| | | | | 13 18 Ether
  192. * ||| | | | | 14 17 Ether
  193. * +++-+---+---+---+- 15 16 Ether
  194. * ++-+---+---+---+- 16 15 PCI_DIS
  195. * +-+---+---+---+- 17 14 USB_SE
  196. * | | | | 18 13 USB
  197. * +---+---+---+- 19 12 USB
  198. * | | | 20 11 PSC3
  199. * | | | 21 10 PSC3
  200. * | | | 22 9 PSC3
  201. * +---+---+- 23 8 PSC3
  202. * | | 24 7 -
  203. * | | 25 6 PSC2
  204. * | | 26 5 PSC2
  205. * +---+- 27 4 PSC2
  206. * | 28 3 -
  207. * | 29 2 PSC1
  208. * | 30 1 PSC1
  209. * +- 31 0 PSC1
  210. */
  211. /*
  212. * Miscellaneous configurable options
  213. */
  214. #define CONFIG_SYS_LONGHELP
  215. #define CONFIG_CMDLINE_EDITING
  216. #define CONFIG_SYS_HUSH_PARSER
  217. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  218. #if defined(CONFIG_CMD_KGDB)
  219. #define CONFIG_SYS_CBSIZE 1024
  220. #else
  221. #define CONFIG_SYS_CBSIZE 256
  222. #endif
  223. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  224. #define CONFIG_SYS_MAXARGS 16
  225. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  226. #define CONFIG_SYS_MEMTEST_START 0x00100000
  227. #define CONFIG_SYS_MEMTEST_END 0x00f00000
  228. #define CONFIG_SYS_LOAD_ADDR 0x00100000
  229. #define CONFIG_LOOPW
  230. #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
  231. /*
  232. * Various low-level settings
  233. */
  234. #define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
  235. #define CONFIG_SYS_HID0_FINAL HID0_ICE
  236. #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
  237. #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
  238. #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
  239. #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
  240. #ifdef CONFIG_A4M2K
  241. /* external MRAM */
  242. #define CONFIG_SYS_CS1_START 0xf1000000
  243. #define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
  244. #endif
  245. #define CONFIG_SYS_CS2_START 0xe0000000
  246. #define CONFIG_SYS_CS2_SIZE 0x00100000
  247. /* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
  248. #define CONFIG_SYS_CS3_START 0xE9000000
  249. #ifdef CONFIG_A4M2K
  250. #define CONFIG_SYS_CS3_SIZE 0x00100000
  251. #else
  252. #define CONFIG_SYS_CS3_SIZE 0x00080000
  253. #endif
  254. /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
  255. #define CONFIG_SYS_CS3_CFG 0x0032B900
  256. #ifndef CONFIG_A4M2K
  257. /* Diagnosis Interface - see ticket #63 */
  258. #define CONFIG_SYS_CS4_START 0xEA000000
  259. #define CONFIG_SYS_CS4_SIZE 0x00000001
  260. /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
  261. #define CONFIG_SYS_CS4_CFG 0x0002B900
  262. #endif
  263. /* FPGA master io (64kiB / 1MiB) - see ticket #66 */
  264. #define CONFIG_SYS_CS5_START 0xE8000000
  265. #ifdef CONFIG_A4M2K
  266. #define CONFIG_SYS_CS5_SIZE 0x00100000
  267. #else
  268. #define CONFIG_SYS_CS5_SIZE 0x00010000
  269. #endif
  270. /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
  271. #define CONFIG_SYS_CS5_CFG 0x0032B900
  272. #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
  273. #define CONFIG_SYS_BOOTCS_CFG 0x0006F900
  274. #define CONFIG_SYS_CS1_CFG 0x0008FD00
  275. #define CONFIG_SYS_CS2_CFG 0x0006F90C
  276. #else /* for pci_clk = 33 MHz */
  277. #define CONFIG_SYS_BOOTCS_CFG 0x0002F900
  278. #define CONFIG_SYS_CS1_CFG 0x0001FB00
  279. #define CONFIG_SYS_CS2_CFG 0x0002F90C
  280. #endif
  281. #define CONFIG_SYS_CS_BURST 0x00000000
  282. /* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
  283. /* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
  284. /* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
  285. #define CONFIG_SYS_CS_DEADCYCLE 0x33030000
  286. #define CONFIG_SYS_RESET_ADDRESS 0xff000000
  287. /*
  288. * Environment Configuration
  289. */
  290. #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
  291. #undef CONFIG_BOOTARGS
  292. #define CONFIG_ZERO_BOOTDELAY_CHECK
  293. #define CONFIG_SYS_AUTOLOAD "n"
  294. #define CONFIG_PREBOOT "echo;" \
  295. "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
  296. "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
  297. "echo"
  298. #undef CONFIG_BOOTARGS
  299. #define CONFIG_SYS_OS_BASE 0xfc200000
  300. #define CONFIG_SYS_FDT_BASE 0xfc1e0000
  301. #define CONFIG_EXTRA_ENV_SETTINGS \
  302. "netdev=eth0\0" \
  303. "verify=no\0" \
  304. "loadaddr=200000\0" \
  305. "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
  306. "kernel_addr_r=1000000\0" \
  307. "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
  308. "fdt_addr_r=1800000\0" \
  309. "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
  310. "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
  311. __stringify(CONFIG_HOSTNAME) ".dtb\0" \
  312. "rootpath=/opt/eldk-5.2.1/powerpc/" \
  313. "core-image-minimal-mtdutils-dropbear-generic\0" \
  314. "consoledev=ttyPSC0\0" \
  315. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  316. "nfsroot=${serverip}:${rootpath}\0" \
  317. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  318. "mtdargs=setenv bootargs root=/dev/mtdblock8 " \
  319. "rootfstype=squashfs,jffs2\0" \
  320. "addhost=setenv bootargs ${bootargs} " \
  321. "hostname=${hostname}\0" \
  322. "addip=setenv bootargs ${bootargs} " \
  323. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  324. ":${hostname}:${netdev}:off panic=1\0" \
  325. "addtty=setenv bootargs ${bootargs} " \
  326. "console=${consoledev},${baudrate}\0" \
  327. "flash_nfs=run nfsargs addip addtty addmtd addhost;" \
  328. "bootm ${kernel_addr} - ${fdt_addr}\0" \
  329. "flash_mtd=run mtdargs addip addtty addmtd addhost;" \
  330. "bootm ${kernel_addr} - ${fdt_addr}\0" \
  331. "flash_self=run ramargs addip addtty addmtd addhost;" \
  332. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  333. "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
  334. "tftp ${fdt_addr_r} ${fdtfile};" \
  335. "run nfsargs addip addtty addmtd addhost;" \
  336. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  337. "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
  338. "/u-boot-img.bin\0" \
  339. "update=protect off fc000000 fc07ffff;" \
  340. "era fc000000 fc07ffff;" \
  341. "cp.b ${loadaddr} fc000000 ${filesize}\0" \
  342. "upd=run load;run update\0" \
  343. "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
  344. "run mtdargs addip addtty addmtd addhost;" \
  345. "fdt addr 1800000;fdt boardsetup;fdt chosen;" \
  346. "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
  347. "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
  348. "erase fc200000 fc6fffff;" \
  349. "cp.b 1000000 fc200000 ${filesize}" \
  350. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  351. "mtdids=" MTDIDS_DEFAULT "\0" \
  352. "mtdparts=" MTDPARTS_DEFAULT "\0" \
  353. ""
  354. #define CONFIG_BOOTCOMMAND "run flash_mtd"
  355. /*
  356. * SPL related defines
  357. */
  358. #define CONFIG_SPL 1
  359. #define CONFIG_SPL_FRAMEWORK
  360. #define CONFIG_SPL_BOARD_INIT
  361. #define CONFIG_SPL_NOR_SUPPORT
  362. #define CONFIG_SPL_TEXT_BASE 0xfc000000
  363. #define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
  364. #define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
  365. #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
  366. #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
  367. #define CONFIG_SPL_SERIAL_SUPPORT
  368. /* Place BSS for SPL near end of SDRAM */
  369. #define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
  370. #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
  371. #define CONFIG_SPL_OS_BOOT
  372. #define CONFIG_SPL_ENV_SUPPORT
  373. /* Place patched DT blob (fdt) at this address */
  374. #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
  375. /* Settings for real U-Boot to be loaded from NOR flash */
  376. #ifndef __ASSEMBLY__
  377. extern char __spl_flash_end[];
  378. #endif
  379. #define CONFIG_SYS_UBOOT_BASE __spl_flash_end
  380. #define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
  381. #define CONFIG_SYS_UBOOT_START 0x1000100
  382. #endif /* __CONFIG_H */