T208xRDB.h 29 KB

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  1. /*
  2. * Copyright 2014 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /*
  7. * T2080 RDB/PCIe board configuration file
  8. */
  9. #ifndef __T2080RDB_H
  10. #define __T2080RDB_H
  11. #define CONFIG_SYS_GENERIC_BOARD
  12. #define CONFIG_DISPLAY_BOARDINFO
  13. #define CONFIG_T2080RDB
  14. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  15. #define CONFIG_MMC
  16. #define CONFIG_SPI_FLASH
  17. #define CONFIG_USB_EHCI
  18. #define CONFIG_FSL_SATA_V2
  19. /* High Level Configuration Options */
  20. #define CONFIG_PHYS_64BIT
  21. #define CONFIG_BOOKE
  22. #define CONFIG_E500 /* BOOKE e500 family */
  23. #define CONFIG_E500MC /* BOOKE e500mc family */
  24. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  25. #define CONFIG_MP /* support multiple processors */
  26. #define CONFIG_ENABLE_36BIT_PHYS
  27. #ifdef CONFIG_PHYS_64BIT
  28. #define CONFIG_ADDR_MAP 1
  29. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  30. #endif
  31. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  32. #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
  33. #define CONFIG_FSL_IFC /* Enable IFC Support */
  34. #define CONFIG_FSL_LAW /* Use common FSL init code */
  35. #define CONFIG_ENV_OVERWRITE
  36. #ifdef CONFIG_RAMBOOT_PBL
  37. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  38. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
  39. #define CONFIG_SPL 1
  40. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  41. #define CONFIG_SPL_ENV_SUPPORT
  42. #define CONFIG_SPL_SERIAL_SUPPORT
  43. #define CONFIG_SPL_FLUSH_IMAGE
  44. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  45. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  46. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  47. #define CONFIG_SPL_I2C_SUPPORT
  48. #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  49. #define CONFIG_FSL_LAW /* Use common FSL init code */
  50. #define CONFIG_SYS_TEXT_BASE 0x00201000
  51. #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
  52. #define CONFIG_SPL_PAD_TO 0x40000
  53. #define CONFIG_SPL_MAX_SIZE 0x28000
  54. #define RESET_VECTOR_OFFSET 0x27FFC
  55. #define BOOT_PAGE_OFFSET 0x27000
  56. #ifdef CONFIG_SPL_BUILD
  57. #define CONFIG_SPL_SKIP_RELOCATE
  58. #define CONFIG_SPL_COMMON_INIT_DDR
  59. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  60. #define CONFIG_SYS_NO_FLASH
  61. #endif
  62. #ifdef CONFIG_NAND
  63. #define CONFIG_SPL_NAND_SUPPORT
  64. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  65. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  66. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  67. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  68. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  69. #define CONFIG_SPL_NAND_BOOT
  70. #endif
  71. #ifdef CONFIG_SPIFLASH
  72. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  73. #define CONFIG_SPL_SPI_SUPPORT
  74. #define CONFIG_SPL_SPI_FLASH_SUPPORT
  75. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  76. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  77. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  78. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  79. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  80. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  81. #ifndef CONFIG_SPL_BUILD
  82. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  83. #endif
  84. #define CONFIG_SPL_SPI_BOOT
  85. #endif
  86. #ifdef CONFIG_SDCARD
  87. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  88. #define CONFIG_SPL_MMC_SUPPORT
  89. #define CONFIG_SPL_MMC_MINIMAL
  90. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  91. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  92. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  93. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  94. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  95. #ifndef CONFIG_SPL_BUILD
  96. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  97. #endif
  98. #define CONFIG_SPL_MMC_BOOT
  99. #endif
  100. #endif /* CONFIG_RAMBOOT_PBL */
  101. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  102. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  103. /* Set 1M boot space */
  104. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  105. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  106. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  107. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  108. #define CONFIG_SYS_NO_FLASH
  109. #endif
  110. #ifndef CONFIG_SYS_TEXT_BASE
  111. #define CONFIG_SYS_TEXT_BASE 0xeff40000
  112. #endif
  113. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  114. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  115. #endif
  116. /*
  117. * These can be toggled for performance analysis, otherwise use default.
  118. */
  119. #define CONFIG_SYS_CACHE_STASHING
  120. #define CONFIG_BTB /* toggle branch predition */
  121. #define CONFIG_DDR_ECC
  122. #ifdef CONFIG_DDR_ECC
  123. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  124. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  125. #endif
  126. #ifndef CONFIG_SYS_NO_FLASH
  127. #define CONFIG_FLASH_CFI_DRIVER
  128. #define CONFIG_SYS_FLASH_CFI
  129. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  130. #endif
  131. #if defined(CONFIG_SPIFLASH)
  132. #define CONFIG_SYS_EXTRA_ENV_RELOC
  133. #define CONFIG_ENV_IS_IN_SPI_FLASH
  134. #define CONFIG_ENV_SPI_BUS 0
  135. #define CONFIG_ENV_SPI_CS 0
  136. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  137. #define CONFIG_ENV_SPI_MODE 0
  138. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  139. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  140. #define CONFIG_ENV_SECT_SIZE 0x10000
  141. #elif defined(CONFIG_SDCARD)
  142. #define CONFIG_SYS_EXTRA_ENV_RELOC
  143. #define CONFIG_ENV_IS_IN_MMC
  144. #define CONFIG_SYS_MMC_ENV_DEV 0
  145. #define CONFIG_ENV_SIZE 0x2000
  146. #define CONFIG_ENV_OFFSET (512 * 0x800)
  147. #elif defined(CONFIG_NAND)
  148. #define CONFIG_SYS_EXTRA_ENV_RELOC
  149. #define CONFIG_ENV_IS_IN_NAND
  150. #define CONFIG_ENV_SIZE 0x2000
  151. #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
  152. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  153. #define CONFIG_ENV_IS_IN_REMOTE
  154. #define CONFIG_ENV_ADDR 0xffe20000
  155. #define CONFIG_ENV_SIZE 0x2000
  156. #elif defined(CONFIG_ENV_IS_NOWHERE)
  157. #define CONFIG_ENV_SIZE 0x2000
  158. #else
  159. #define CONFIG_ENV_IS_IN_FLASH
  160. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  161. #define CONFIG_ENV_SIZE 0x2000
  162. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  163. #endif
  164. #ifndef __ASSEMBLY__
  165. unsigned long get_board_sys_clk(void);
  166. unsigned long get_board_ddr_clk(void);
  167. #endif
  168. #define CONFIG_SYS_CLK_FREQ 66660000
  169. #define CONFIG_DDR_CLK_FREQ 133330000
  170. /*
  171. * Config the L3 Cache as L3 SRAM
  172. */
  173. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  174. #define CONFIG_SYS_L3_SIZE (512 << 10)
  175. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  176. #ifdef CONFIG_RAMBOOT_PBL
  177. #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  178. #endif
  179. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  180. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  181. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  182. #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
  183. #define CONFIG_SYS_DCSRBAR 0xf0000000
  184. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  185. /* EEPROM */
  186. #define CONFIG_ID_EEPROM
  187. #define CONFIG_SYS_I2C_EEPROM_NXID
  188. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  189. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  190. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  191. /*
  192. * DDR Setup
  193. */
  194. #define CONFIG_VERY_BIG_RAM
  195. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  196. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  197. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  198. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  199. #define CONFIG_DDR_SPD
  200. #define CONFIG_SYS_FSL_DDR3
  201. #undef CONFIG_FSL_DDR_INTERACTIVE
  202. #define CONFIG_SYS_SPD_BUS_NUM 0
  203. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  204. #define SPD_EEPROM_ADDRESS1 0x51
  205. #define SPD_EEPROM_ADDRESS2 0x52
  206. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  207. #define CTRL_INTLV_PREFERED cacheline
  208. /*
  209. * IFC Definitions
  210. */
  211. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  212. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  213. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  214. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  215. CSPR_PORT_SIZE_16 | \
  216. CSPR_MSEL_NOR | \
  217. CSPR_V)
  218. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  219. /* NOR Flash Timing Params */
  220. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  221. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  222. FTIM0_NOR_TEADC(0x5) | \
  223. FTIM0_NOR_TEAHC(0x5))
  224. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  225. FTIM1_NOR_TRAD_NOR(0x1A) |\
  226. FTIM1_NOR_TSEQRAD_NOR(0x13))
  227. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  228. FTIM2_NOR_TCH(0x4) | \
  229. FTIM2_NOR_TWPH(0x0E) | \
  230. FTIM2_NOR_TWP(0x1c))
  231. #define CONFIG_SYS_NOR_FTIM3 0x0
  232. #define CONFIG_SYS_FLASH_QUIET_TEST
  233. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  234. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  235. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  236. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  237. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  238. #define CONFIG_SYS_FLASH_EMPTY_INFO
  239. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
  240. /* CPLD on IFC */
  241. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  242. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  243. #define CONFIG_SYS_CSPR2_EXT (0xf)
  244. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
  245. | CSPR_PORT_SIZE_8 \
  246. | CSPR_MSEL_GPCM \
  247. | CSPR_V)
  248. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  249. #define CONFIG_SYS_CSOR2 0x0
  250. /* CPLD Timing parameters for IFC CS2 */
  251. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  252. FTIM0_GPCM_TEADC(0x0e) | \
  253. FTIM0_GPCM_TEAHC(0x0e))
  254. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  255. FTIM1_GPCM_TRAD(0x1f))
  256. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  257. FTIM2_GPCM_TCH(0x8) | \
  258. FTIM2_GPCM_TWP(0x1f))
  259. #define CONFIG_SYS_CS2_FTIM3 0x0
  260. /* NAND Flash on IFC */
  261. #define CONFIG_NAND_FSL_IFC
  262. #define CONFIG_SYS_NAND_BASE 0xff800000
  263. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  264. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  265. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  266. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  267. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  268. | CSPR_V)
  269. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  270. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  271. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  272. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  273. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  274. | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  275. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  276. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  277. #define CONFIG_SYS_NAND_ONFI_DETECTION
  278. /* ONFI NAND Flash mode0 Timing Params */
  279. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  280. FTIM0_NAND_TWP(0x18) | \
  281. FTIM0_NAND_TWCHT(0x07) | \
  282. FTIM0_NAND_TWH(0x0a))
  283. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  284. FTIM1_NAND_TWBE(0x39) | \
  285. FTIM1_NAND_TRR(0x0e) | \
  286. FTIM1_NAND_TRP(0x18))
  287. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  288. FTIM2_NAND_TREH(0x0a) | \
  289. FTIM2_NAND_TWHRE(0x1e))
  290. #define CONFIG_SYS_NAND_FTIM3 0x0
  291. #define CONFIG_SYS_NAND_DDR_LAW 11
  292. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  293. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  294. #define CONFIG_MTD_NAND_VERIFY_WRITE
  295. #define CONFIG_CMD_NAND
  296. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  297. #if defined(CONFIG_NAND)
  298. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  299. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  300. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  301. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  302. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  303. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  304. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  305. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  306. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  307. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  308. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  309. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  310. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  311. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  312. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  313. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  314. #else
  315. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  316. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  317. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  318. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  319. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  320. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  321. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  322. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  323. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  324. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  325. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  326. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  327. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  328. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  329. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  330. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  331. #endif
  332. #if defined(CONFIG_RAMBOOT_PBL)
  333. #define CONFIG_SYS_RAMBOOT
  334. #endif
  335. #ifdef CONFIG_SPL_BUILD
  336. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  337. #else
  338. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  339. #endif
  340. #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  341. #define CONFIG_MISC_INIT_R
  342. #define CONFIG_HWCONFIG
  343. /* define to use L1 as initial stack */
  344. #define CONFIG_L1_INIT_RAM
  345. #define CONFIG_SYS_INIT_RAM_LOCK
  346. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  347. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  348. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
  349. /* The assembler doesn't like typecast */
  350. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  351. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  352. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  353. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  354. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  355. GENERATED_GBL_DATA_SIZE)
  356. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  357. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  358. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  359. /*
  360. * Serial Port
  361. */
  362. #define CONFIG_CONS_INDEX 1
  363. #define CONFIG_SYS_NS16550
  364. #define CONFIG_SYS_NS16550_SERIAL
  365. #define CONFIG_SYS_NS16550_REG_SIZE 1
  366. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  367. #define CONFIG_SYS_BAUDRATE_TABLE \
  368. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  369. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  370. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  371. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  372. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  373. /* Use the HUSH parser */
  374. #define CONFIG_SYS_HUSH_PARSER
  375. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  376. /* pass open firmware flat tree */
  377. #define CONFIG_OF_LIBFDT
  378. #define CONFIG_OF_BOARD_SETUP
  379. #define CONFIG_OF_STDOUT_VIA_ALIAS
  380. /* new uImage format support */
  381. #define CONFIG_FIT
  382. #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  383. /*
  384. * I2C
  385. */
  386. #define CONFIG_SYS_I2C
  387. #define CONFIG_SYS_I2C_FSL
  388. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  389. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  390. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  391. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  392. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  393. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  394. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  395. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  396. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  397. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  398. #define CONFIG_SYS_FSL_I2C3_SPEED 100000
  399. #define CONFIG_SYS_FSL_I2C4_SPEED 100000
  400. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  401. #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  402. #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  403. #define I2C_MUX_CH_DEFAULT 0x8
  404. /*
  405. * RapidIO
  406. */
  407. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  408. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  409. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  410. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  411. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  412. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  413. /*
  414. * for slave u-boot IMAGE instored in master memory space,
  415. * PHYS must be aligned based on the SIZE
  416. */
  417. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  418. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  419. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  420. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  421. /*
  422. * for slave UCODE and ENV instored in master memory space,
  423. * PHYS must be aligned based on the SIZE
  424. */
  425. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  426. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  427. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  428. /* slave core release by master*/
  429. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  430. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  431. /*
  432. * SRIO_PCIE_BOOT - SLAVE
  433. */
  434. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  435. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  436. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  437. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  438. #endif
  439. /*
  440. * eSPI - Enhanced SPI
  441. */
  442. #ifdef CONFIG_SPI_FLASH
  443. #define CONFIG_FSL_ESPI
  444. #define CONFIG_SPI_FLASH_STMICRO
  445. #define CONFIG_SPI_FLASH_BAR
  446. #define CONFIG_CMD_SF
  447. #define CONFIG_SF_DEFAULT_SPEED 10000000
  448. #define CONFIG_SF_DEFAULT_MODE 0
  449. #endif
  450. /*
  451. * General PCI
  452. * Memory space is mapped 1-1, but I/O space must start from 0.
  453. */
  454. #define CONFIG_PCI /* Enable PCI/PCIE */
  455. #define CONFIG_PCIE1 /* PCIE controler 1 */
  456. #define CONFIG_PCIE2 /* PCIE controler 2 */
  457. #define CONFIG_PCIE3 /* PCIE controler 3 */
  458. #define CONFIG_PCIE4 /* PCIE controler 4 */
  459. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  460. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  461. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  462. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  463. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  464. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  465. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  466. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  467. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  468. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  469. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  470. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  471. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  472. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  473. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  474. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  475. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  476. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  477. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  478. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  479. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  480. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  481. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  482. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  483. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  484. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  485. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  486. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  487. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  488. /* controller 4, Base address 203000 */
  489. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  490. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  491. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  492. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  493. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  494. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  495. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  496. #ifdef CONFIG_PCI
  497. #define CONFIG_PCI_INDIRECT_BRIDGE
  498. #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
  499. #define CONFIG_NET_MULTI
  500. #define CONFIG_E1000
  501. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  502. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  503. #define CONFIG_DOS_PARTITION
  504. #endif
  505. /* Qman/Bman */
  506. #ifndef CONFIG_NOBQFMAN
  507. #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
  508. #define CONFIG_SYS_BMAN_NUM_PORTALS 18
  509. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  510. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  511. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  512. #define CONFIG_SYS_QMAN_NUM_PORTALS 18
  513. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  514. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  515. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  516. #define CONFIG_SYS_DPAA_FMAN
  517. #define CONFIG_SYS_DPAA_PME
  518. #define CONFIG_SYS_PMAN
  519. #define CONFIG_SYS_DPAA_DCE
  520. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  521. #define CONFIG_SYS_INTERLAKEN
  522. /* Default address of microcode for the Linux Fman driver */
  523. #if defined(CONFIG_SPIFLASH)
  524. /*
  525. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  526. * env, so we got 0x110000.
  527. */
  528. #define CONFIG_SYS_QE_FW_IN_SPIFLASH
  529. #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
  530. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  531. #define CONFIG_CORTINA_FW_ADDR 0x120000
  532. #elif defined(CONFIG_SDCARD)
  533. /*
  534. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  535. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  536. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  537. */
  538. #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  539. #define CONFIG_SYS_CORTINA_FW_IN_MMC
  540. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  541. #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
  542. #elif defined(CONFIG_NAND)
  543. #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  544. #define CONFIG_SYS_CORTINA_FW_IN_NAND
  545. #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
  546. #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
  547. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  548. /*
  549. * Slave has no ucode locally, it can fetch this from remote. When implementing
  550. * in two corenet boards, slave's ucode could be stored in master's memory
  551. * space, the address can be mapped from slave TLB->slave LAW->
  552. * slave SRIO or PCIE outbound window->master inbound window->
  553. * master LAW->the ucode address in master's memory space.
  554. */
  555. #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
  556. #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
  557. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  558. #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
  559. #else
  560. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  561. #define CONFIG_SYS_CORTINA_FW_IN_NOR
  562. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  563. #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
  564. #endif
  565. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  566. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  567. #endif /* CONFIG_NOBQFMAN */
  568. #ifdef CONFIG_SYS_DPAA_FMAN
  569. #define CONFIG_FMAN_ENET
  570. #define CONFIG_PHYLIB_10G
  571. #define CONFIG_PHY_CORTINA
  572. #define CONFIG_PHY_AQ1202
  573. #define CONFIG_PHY_REALTEK
  574. #define CONFIG_CORTINA_FW_LENGTH 0x40000
  575. #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
  576. #define RGMII_PHY2_ADDR 0x02
  577. #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
  578. #define CORTINA_PHY_ADDR2 0x0d
  579. #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
  580. #define FM1_10GEC4_PHY_ADDR 0x01
  581. #endif
  582. #ifdef CONFIG_FMAN_ENET
  583. #define CONFIG_MII /* MII PHY management */
  584. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  585. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  586. #endif
  587. /*
  588. * SATA
  589. */
  590. #ifdef CONFIG_FSL_SATA_V2
  591. #define CONFIG_LIBATA
  592. #define CONFIG_FSL_SATA
  593. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  594. #define CONFIG_SATA1
  595. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  596. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  597. #define CONFIG_SATA2
  598. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  599. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  600. #define CONFIG_LBA48
  601. #define CONFIG_CMD_SATA
  602. #define CONFIG_DOS_PARTITION
  603. #define CONFIG_CMD_EXT2
  604. #endif
  605. /*
  606. * USB
  607. */
  608. #ifdef CONFIG_USB_EHCI
  609. #define CONFIG_CMD_USB
  610. #define CONFIG_USB_STORAGE
  611. #define CONFIG_USB_EHCI_FSL
  612. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  613. #define CONFIG_CMD_EXT2
  614. #define CONFIG_HAS_FSL_DR_USB
  615. #endif
  616. /*
  617. * SDHC
  618. */
  619. #ifdef CONFIG_MMC
  620. #define CONFIG_CMD_MMC
  621. #define CONFIG_FSL_ESDHC
  622. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  623. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  624. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  625. #define CONFIG_GENERIC_MMC
  626. #define CONFIG_CMD_EXT2
  627. #define CONFIG_CMD_FAT
  628. #define CONFIG_DOS_PARTITION
  629. #endif
  630. /*
  631. * Dynamic MTD Partition support with mtdparts
  632. */
  633. #ifndef CONFIG_SYS_NO_FLASH
  634. #define CONFIG_MTD_DEVICE
  635. #define CONFIG_MTD_PARTITIONS
  636. #define CONFIG_CMD_MTDPARTS
  637. #define CONFIG_FLASH_CFI_MTD
  638. #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
  639. "spi0=spife110000.1"
  640. #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
  641. "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
  642. "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
  643. "1m(uboot),5m(kernel),128k(dtb),-(user)"
  644. #endif
  645. /*
  646. * Environment
  647. */
  648. /*
  649. * Command line configuration.
  650. */
  651. #include <config_cmd_default.h>
  652. #define CONFIG_CMD_DHCP
  653. #define CONFIG_CMD_ELF
  654. #define CONFIG_CMD_ERRATA
  655. #define CONFIG_CMD_MII
  656. #define CONFIG_CMD_I2C
  657. #define CONFIG_CMD_PING
  658. #define CONFIG_CMD_ECHO
  659. #define CONFIG_CMD_SETEXPR
  660. #define CONFIG_CMD_REGINFO
  661. #define CONFIG_CMD_BDI
  662. #ifdef CONFIG_PCI
  663. #define CONFIG_CMD_PCI
  664. #define CONFIG_CMD_NET
  665. #endif
  666. /*
  667. * Miscellaneous configurable options
  668. */
  669. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  670. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  671. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  672. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  673. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  674. #ifdef CONFIG_CMD_KGDB
  675. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  676. #else
  677. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  678. #endif
  679. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  680. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  681. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  682. /*
  683. * For booting Linux, the board info and command line data
  684. * have to be in the first 64 MB of memory, since this is
  685. * the maximum mapped by the Linux kernel during initialization.
  686. */
  687. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  688. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  689. #ifdef CONFIG_CMD_KGDB
  690. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  691. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  692. #endif
  693. /*
  694. * Environment Configuration
  695. */
  696. #define CONFIG_ROOTPATH "/opt/nfsroot"
  697. #define CONFIG_BOOTFILE "uImage"
  698. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  699. /* default location for tftp and bootm */
  700. #define CONFIG_LOADADDR 1000000
  701. #define CONFIG_BAUDRATE 115200
  702. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  703. #define __USB_PHY_TYPE utmi
  704. #define CONFIG_EXTRA_ENV_SETTINGS \
  705. "hwconfig=fsl_ddr:" \
  706. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  707. "bank_intlv=auto;" \
  708. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  709. "netdev=eth0\0" \
  710. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  711. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  712. "tftpflash=tftpboot $loadaddr $uboot && " \
  713. "protect off $ubootaddr +$filesize && " \
  714. "erase $ubootaddr +$filesize && " \
  715. "cp.b $loadaddr $ubootaddr $filesize && " \
  716. "protect on $ubootaddr +$filesize && " \
  717. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  718. "consoledev=ttyS0\0" \
  719. "ramdiskaddr=2000000\0" \
  720. "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
  721. "fdtaddr=c00000\0" \
  722. "fdtfile=t2080rdb/t2080rdb.dtb\0" \
  723. "bdev=sda3\0"
  724. /*
  725. * For emulation this causes u-boot to jump to the start of the
  726. * proof point app code automatically
  727. */
  728. #define CONFIG_PROOF_POINTS \
  729. "setenv bootargs root=/dev/$bdev rw " \
  730. "console=$consoledev,$baudrate $othbootargs;" \
  731. "cpu 1 release 0x29000000 - - -;" \
  732. "cpu 2 release 0x29000000 - - -;" \
  733. "cpu 3 release 0x29000000 - - -;" \
  734. "cpu 4 release 0x29000000 - - -;" \
  735. "cpu 5 release 0x29000000 - - -;" \
  736. "cpu 6 release 0x29000000 - - -;" \
  737. "cpu 7 release 0x29000000 - - -;" \
  738. "go 0x29000000"
  739. #define CONFIG_HVBOOT \
  740. "setenv bootargs config-addr=0x60000000; " \
  741. "bootm 0x01000000 - 0x00f00000"
  742. #define CONFIG_ALU \
  743. "setenv bootargs root=/dev/$bdev rw " \
  744. "console=$consoledev,$baudrate $othbootargs;" \
  745. "cpu 1 release 0x01000000 - - -;" \
  746. "cpu 2 release 0x01000000 - - -;" \
  747. "cpu 3 release 0x01000000 - - -;" \
  748. "cpu 4 release 0x01000000 - - -;" \
  749. "cpu 5 release 0x01000000 - - -;" \
  750. "cpu 6 release 0x01000000 - - -;" \
  751. "cpu 7 release 0x01000000 - - -;" \
  752. "go 0x01000000"
  753. #define CONFIG_LINUX \
  754. "setenv bootargs root=/dev/ram rw " \
  755. "console=$consoledev,$baudrate $othbootargs;" \
  756. "setenv ramdiskaddr 0x02000000;" \
  757. "setenv fdtaddr 0x00c00000;" \
  758. "setenv loadaddr 0x1000000;" \
  759. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  760. #define CONFIG_HDBOOT \
  761. "setenv bootargs root=/dev/$bdev rw " \
  762. "console=$consoledev,$baudrate $othbootargs;" \
  763. "tftp $loadaddr $bootfile;" \
  764. "tftp $fdtaddr $fdtfile;" \
  765. "bootm $loadaddr - $fdtaddr"
  766. #define CONFIG_NFSBOOTCOMMAND \
  767. "setenv bootargs root=/dev/nfs rw " \
  768. "nfsroot=$serverip:$rootpath " \
  769. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  770. "console=$consoledev,$baudrate $othbootargs;" \
  771. "tftp $loadaddr $bootfile;" \
  772. "tftp $fdtaddr $fdtfile;" \
  773. "bootm $loadaddr - $fdtaddr"
  774. #define CONFIG_RAMBOOTCOMMAND \
  775. "setenv bootargs root=/dev/ram rw " \
  776. "console=$consoledev,$baudrate $othbootargs;" \
  777. "tftp $ramdiskaddr $ramdiskfile;" \
  778. "tftp $loadaddr $bootfile;" \
  779. "tftp $fdtaddr $fdtfile;" \
  780. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  781. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  782. #ifdef CONFIG_SECURE_BOOT
  783. #include <asm/fsl_secure_boot.h>
  784. #undef CONFIG_CMD_USB
  785. #endif
  786. #endif /* __T2080RDB_H */