T104xRDB.h 26 KB

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  1. /*
  2. + * Copyright 2014 Freescale Semiconductor, Inc.
  3. + *
  4. + * SPDX-License-Identifier: GPL-2.0+
  5. + */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. /*
  9. * T104x RDB board configuration file
  10. */
  11. #define CONFIG_T104xRDB
  12. #define CONFIG_PHYS_64BIT
  13. #ifdef CONFIG_RAMBOOT_PBL
  14. #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  15. #ifdef CONFIG_T1040RDB
  16. #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
  17. #endif
  18. #ifdef CONFIG_T1042RDB_PI
  19. #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
  20. #endif
  21. #define CONFIG_SPL 1
  22. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  23. #define CONFIG_SPL_ENV_SUPPORT
  24. #define CONFIG_SPL_SERIAL_SUPPORT
  25. #define CONFIG_SPL_FLUSH_IMAGE
  26. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  27. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  28. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  29. #define CONFIG_SPL_I2C_SUPPORT
  30. #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  31. #define CONFIG_FSL_LAW /* Use common FSL init code */
  32. #define CONFIG_SYS_TEXT_BASE 0x00201000
  33. #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
  34. #define CONFIG_SPL_PAD_TO 0x40000
  35. #define CONFIG_SPL_MAX_SIZE 0x28000
  36. #ifdef CONFIG_SPL_BUILD
  37. #define CONFIG_SPL_SKIP_RELOCATE
  38. #define CONFIG_SPL_COMMON_INIT_DDR
  39. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  40. #define CONFIG_SYS_NO_FLASH
  41. #endif
  42. #define RESET_VECTOR_OFFSET 0x27FFC
  43. #define BOOT_PAGE_OFFSET 0x27000
  44. #ifdef CONFIG_NAND
  45. #define CONFIG_SPL_NAND_SUPPORT
  46. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  47. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  48. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  49. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  50. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  51. #define CONFIG_SPL_NAND_BOOT
  52. #endif
  53. #ifdef CONFIG_SPIFLASH
  54. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  55. #define CONFIG_SPL_SPI_SUPPORT
  56. #define CONFIG_SPL_SPI_FLASH_SUPPORT
  57. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  58. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  59. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  60. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  61. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  62. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  63. #ifndef CONFIG_SPL_BUILD
  64. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  65. #endif
  66. #define CONFIG_SPL_SPI_BOOT
  67. #endif
  68. #ifdef CONFIG_SDCARD
  69. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  70. #define CONFIG_SPL_MMC_SUPPORT
  71. #define CONFIG_SPL_MMC_MINIMAL
  72. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  73. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  74. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  75. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  76. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  77. #ifndef CONFIG_SPL_BUILD
  78. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  79. #endif
  80. #define CONFIG_SPL_MMC_BOOT
  81. #endif
  82. #endif
  83. /* High Level Configuration Options */
  84. #define CONFIG_BOOKE
  85. #define CONFIG_E500 /* BOOKE e500 family */
  86. #define CONFIG_E500MC /* BOOKE e500mc family */
  87. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  88. #define CONFIG_MP /* support multiple processors */
  89. /* support deep sleep */
  90. #define CONFIG_DEEP_SLEEP
  91. #define CONFIG_SILENT_CONSOLE
  92. #ifndef CONFIG_SYS_TEXT_BASE
  93. #define CONFIG_SYS_TEXT_BASE 0xeff40000
  94. #endif
  95. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  96. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  97. #endif
  98. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  99. #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
  100. #define CONFIG_FSL_IFC /* Enable IFC Support */
  101. #define CONFIG_PCI /* Enable PCI/PCIE */
  102. #define CONFIG_PCI_INDIRECT_BRIDGE
  103. #define CONFIG_PCIE1 /* PCIE controler 1 */
  104. #define CONFIG_PCIE2 /* PCIE controler 2 */
  105. #define CONFIG_PCIE3 /* PCIE controler 3 */
  106. #define CONFIG_PCIE4 /* PCIE controler 4 */
  107. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  108. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  109. #define CONFIG_FSL_LAW /* Use common FSL init code */
  110. #define CONFIG_ENV_OVERWRITE
  111. #ifndef CONFIG_SYS_NO_FLASH
  112. #define CONFIG_FLASH_CFI_DRIVER
  113. #define CONFIG_SYS_FLASH_CFI
  114. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  115. #endif
  116. #if defined(CONFIG_SPIFLASH)
  117. #define CONFIG_SYS_EXTRA_ENV_RELOC
  118. #define CONFIG_ENV_IS_IN_SPI_FLASH
  119. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  120. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  121. #define CONFIG_ENV_SECT_SIZE 0x10000
  122. #elif defined(CONFIG_SDCARD)
  123. #define CONFIG_SYS_EXTRA_ENV_RELOC
  124. #define CONFIG_ENV_IS_IN_MMC
  125. #define CONFIG_SYS_MMC_ENV_DEV 0
  126. #define CONFIG_ENV_SIZE 0x2000
  127. #define CONFIG_ENV_OFFSET (512 * 0x800)
  128. #elif defined(CONFIG_NAND)
  129. #define CONFIG_SYS_EXTRA_ENV_RELOC
  130. #define CONFIG_ENV_IS_IN_NAND
  131. #define CONFIG_ENV_SIZE 0x2000
  132. #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
  133. #else
  134. #define CONFIG_ENV_IS_IN_FLASH
  135. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  136. #define CONFIG_ENV_SIZE 0x2000
  137. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  138. #endif
  139. #define CONFIG_SYS_CLK_FREQ 100000000
  140. #define CONFIG_DDR_CLK_FREQ 66666666
  141. /*
  142. * These can be toggled for performance analysis, otherwise use default.
  143. */
  144. #define CONFIG_SYS_CACHE_STASHING
  145. #define CONFIG_BACKSIDE_L2_CACHE
  146. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  147. #define CONFIG_BTB /* toggle branch predition */
  148. #define CONFIG_DDR_ECC
  149. #ifdef CONFIG_DDR_ECC
  150. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  151. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  152. #endif
  153. #define CONFIG_ENABLE_36BIT_PHYS
  154. #define CONFIG_ADDR_MAP
  155. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  156. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  157. #define CONFIG_SYS_MEMTEST_END 0x00400000
  158. #define CONFIG_SYS_ALT_MEMTEST
  159. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  160. /*
  161. * Config the L3 Cache as L3 SRAM
  162. */
  163. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  164. #define CONFIG_SYS_L3_SIZE 256 << 10
  165. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  166. #ifdef CONFIG_RAMBOOT_PBL
  167. #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  168. #endif
  169. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  170. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  171. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  172. #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
  173. #define CONFIG_SYS_DCSRBAR 0xf0000000
  174. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  175. /*
  176. * DDR Setup
  177. */
  178. #define CONFIG_VERY_BIG_RAM
  179. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  180. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  181. /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
  182. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  183. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  184. #define CONFIG_DDR_SPD
  185. #define CONFIG_SYS_DDR_RAW_TIMING
  186. #define CONFIG_SYS_FSL_DDR3
  187. #define CONFIG_SYS_SPD_BUS_NUM 0
  188. #define SPD_EEPROM_ADDRESS 0x51
  189. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  190. /*
  191. * IFC Definitions
  192. */
  193. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  194. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  195. #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
  196. #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
  197. CSPR_PORT_SIZE_16 | \
  198. CSPR_MSEL_NOR | \
  199. CSPR_V)
  200. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  201. /*
  202. * TDM Definition
  203. */
  204. #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
  205. /* NOR Flash Timing Params */
  206. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  207. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  208. FTIM0_NOR_TEADC(0x5) | \
  209. FTIM0_NOR_TEAHC(0x5))
  210. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  211. FTIM1_NOR_TRAD_NOR(0x1A) |\
  212. FTIM1_NOR_TSEQRAD_NOR(0x13))
  213. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  214. FTIM2_NOR_TCH(0x4) | \
  215. FTIM2_NOR_TWPH(0x0E) | \
  216. FTIM2_NOR_TWP(0x1c))
  217. #define CONFIG_SYS_NOR_FTIM3 0x0
  218. #define CONFIG_SYS_FLASH_QUIET_TEST
  219. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  220. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  221. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  222. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  223. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  224. #define CONFIG_SYS_FLASH_EMPTY_INFO
  225. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  226. /* CPLD on IFC */
  227. #define CPLD_LBMAP_MASK 0x3F
  228. #define CPLD_BANK_SEL_MASK 0x07
  229. #define CPLD_BANK_OVERRIDE 0x40
  230. #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
  231. #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
  232. #define CPLD_LBMAP_RESET 0xFF
  233. #define CPLD_LBMAP_SHIFT 0x03
  234. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  235. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  236. #define CONFIG_SYS_CSPR2_EXT (0xf)
  237. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  238. | CSPR_PORT_SIZE_8 \
  239. | CSPR_MSEL_GPCM \
  240. | CSPR_V)
  241. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  242. #define CONFIG_SYS_CSOR2 0x0
  243. /* CPLD Timing parameters for IFC CS2 */
  244. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  245. FTIM0_GPCM_TEADC(0x0e) | \
  246. FTIM0_GPCM_TEAHC(0x0e))
  247. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  248. FTIM1_GPCM_TRAD(0x1f))
  249. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  250. FTIM2_GPCM_TCH(0x8) | \
  251. FTIM2_GPCM_TWP(0x1f))
  252. #define CONFIG_SYS_CS2_FTIM3 0x0
  253. /* NAND Flash on IFC */
  254. #define CONFIG_NAND_FSL_IFC
  255. #define CONFIG_SYS_NAND_BASE 0xff800000
  256. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  257. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  258. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  259. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  260. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  261. | CSPR_V)
  262. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  263. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  264. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  265. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  266. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  267. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  268. | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
  269. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  270. #define CONFIG_SYS_NAND_ONFI_DETECTION
  271. /* ONFI NAND Flash mode0 Timing Params */
  272. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  273. FTIM0_NAND_TWP(0x18) | \
  274. FTIM0_NAND_TWCHT(0x07) | \
  275. FTIM0_NAND_TWH(0x0a))
  276. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  277. FTIM1_NAND_TWBE(0x39) | \
  278. FTIM1_NAND_TRR(0x0e) | \
  279. FTIM1_NAND_TRP(0x18))
  280. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  281. FTIM2_NAND_TREH(0x0a) | \
  282. FTIM2_NAND_TWHRE(0x1e))
  283. #define CONFIG_SYS_NAND_FTIM3 0x0
  284. #define CONFIG_SYS_NAND_DDR_LAW 11
  285. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  286. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  287. #define CONFIG_MTD_NAND_VERIFY_WRITE
  288. #define CONFIG_CMD_NAND
  289. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  290. #if defined(CONFIG_NAND)
  291. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  292. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  293. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  294. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  295. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  296. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  297. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  298. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  299. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
  300. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  301. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  302. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  303. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  304. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  305. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  306. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  307. #else
  308. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  309. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  310. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  311. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  312. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  313. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  314. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  315. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  316. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  317. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  318. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  319. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  320. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  321. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  322. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  323. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  324. #endif
  325. #ifdef CONFIG_SPL_BUILD
  326. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  327. #else
  328. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  329. #endif
  330. #if defined(CONFIG_RAMBOOT_PBL)
  331. #define CONFIG_SYS_RAMBOOT
  332. #endif
  333. #define CONFIG_BOARD_EARLY_INIT_R
  334. #define CONFIG_MISC_INIT_R
  335. #define CONFIG_HWCONFIG
  336. /* define to use L1 as initial stack */
  337. #define CONFIG_L1_INIT_RAM
  338. #define CONFIG_SYS_INIT_RAM_LOCK
  339. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  340. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  341. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
  342. /* The assembler doesn't like typecast */
  343. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  344. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  345. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  346. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  347. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  348. GENERATED_GBL_DATA_SIZE)
  349. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  350. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  351. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  352. /* Serial Port - controlled on board with jumper J8
  353. * open - index 2
  354. * shorted - index 1
  355. */
  356. #define CONFIG_CONS_INDEX 1
  357. #define CONFIG_SYS_NS16550
  358. #define CONFIG_SYS_NS16550_SERIAL
  359. #define CONFIG_SYS_NS16550_REG_SIZE 1
  360. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  361. #define CONFIG_SYS_BAUDRATE_TABLE \
  362. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  363. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  364. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  365. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  366. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  367. #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
  368. #ifndef CONFIG_SPL_BUILD
  369. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
  370. #endif
  371. /* Use the HUSH parser */
  372. #define CONFIG_SYS_HUSH_PARSER
  373. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  374. /* pass open firmware flat tree */
  375. #define CONFIG_OF_LIBFDT
  376. #define CONFIG_OF_BOARD_SETUP
  377. #define CONFIG_OF_STDOUT_VIA_ALIAS
  378. /* new uImage format support */
  379. #define CONFIG_FIT
  380. #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  381. /* I2C */
  382. #define CONFIG_SYS_I2C
  383. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  384. #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
  385. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  386. #define CONFIG_SYS_FSL_I2C3_SPEED 400000
  387. #define CONFIG_SYS_FSL_I2C4_SPEED 400000
  388. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  389. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  390. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  391. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  392. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  393. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  394. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  395. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  396. /* I2C bus multiplexer */
  397. #define I2C_MUX_PCA_ADDR 0x70
  398. #ifdef CONFIG_T1040RDB
  399. #define I2C_MUX_CH_DEFAULT 0x8
  400. #endif
  401. #ifdef CONFIG_T1042RDB_PI
  402. /*
  403. * RTC configuration
  404. */
  405. #define RTC
  406. #define CONFIG_RTC_DS1337 1
  407. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  408. /*DVI encoder*/
  409. #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
  410. #endif
  411. /*
  412. * eSPI - Enhanced SPI
  413. */
  414. #define CONFIG_FSL_ESPI
  415. #define CONFIG_SPI_FLASH
  416. #define CONFIG_SPI_FLASH_STMICRO
  417. #define CONFIG_CMD_SF
  418. #define CONFIG_SF_DEFAULT_SPEED 10000000
  419. #define CONFIG_SF_DEFAULT_MODE 0
  420. #define CONFIG_ENV_SPI_BUS 0
  421. #define CONFIG_ENV_SPI_CS 0
  422. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  423. #define CONFIG_ENV_SPI_MODE 0
  424. /*
  425. * General PCI
  426. * Memory space is mapped 1-1, but I/O space must start from 0.
  427. */
  428. #ifdef CONFIG_PCI
  429. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  430. #ifdef CONFIG_PCIE1
  431. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  432. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  433. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  434. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  435. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  436. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  437. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  438. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  439. #endif
  440. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  441. #ifdef CONFIG_PCIE2
  442. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  443. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  444. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  445. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  446. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  447. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  448. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  449. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  450. #endif
  451. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  452. #ifdef CONFIG_PCIE3
  453. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  454. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  455. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  456. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  457. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  458. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  459. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  460. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  461. #endif
  462. /* controller 4, Base address 203000 */
  463. #ifdef CONFIG_PCIE4
  464. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
  465. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  466. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
  467. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  468. #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
  469. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  470. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  471. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  472. #endif
  473. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  474. #define CONFIG_E1000
  475. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  476. #define CONFIG_DOS_PARTITION
  477. #endif /* CONFIG_PCI */
  478. /* SATA */
  479. #define CONFIG_FSL_SATA_V2
  480. #ifdef CONFIG_FSL_SATA_V2
  481. #define CONFIG_LIBATA
  482. #define CONFIG_FSL_SATA
  483. #define CONFIG_SYS_SATA_MAX_DEVICE 1
  484. #define CONFIG_SATA1
  485. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  486. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  487. #define CONFIG_LBA48
  488. #define CONFIG_CMD_SATA
  489. #define CONFIG_DOS_PARTITION
  490. #define CONFIG_CMD_EXT2
  491. #endif
  492. /*
  493. * USB
  494. */
  495. #define CONFIG_HAS_FSL_DR_USB
  496. #ifdef CONFIG_HAS_FSL_DR_USB
  497. #define CONFIG_USB_EHCI
  498. #ifdef CONFIG_USB_EHCI
  499. #define CONFIG_CMD_USB
  500. #define CONFIG_USB_STORAGE
  501. #define CONFIG_USB_EHCI_FSL
  502. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  503. #define CONFIG_CMD_EXT2
  504. #endif
  505. #endif
  506. #define CONFIG_MMC
  507. #ifdef CONFIG_MMC
  508. #define CONFIG_FSL_ESDHC
  509. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  510. #define CONFIG_CMD_MMC
  511. #define CONFIG_GENERIC_MMC
  512. #define CONFIG_CMD_EXT2
  513. #define CONFIG_CMD_FAT
  514. #define CONFIG_DOS_PARTITION
  515. #endif
  516. /* Qman/Bman */
  517. #ifndef CONFIG_NOBQFMAN
  518. #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
  519. #define CONFIG_SYS_BMAN_NUM_PORTALS 25
  520. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  521. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  522. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  523. #define CONFIG_SYS_QMAN_NUM_PORTALS 25
  524. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  525. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  526. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  527. #define CONFIG_SYS_DPAA_FMAN
  528. #define CONFIG_SYS_DPAA_PME
  529. #ifdef CONFIG_T1040RDB
  530. #define CONFIG_QE
  531. #define CONFIG_U_QE
  532. #endif
  533. /* Default address of microcode for the Linux Fman driver */
  534. #if defined(CONFIG_SPIFLASH)
  535. /*
  536. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  537. * env, so we got 0x110000.
  538. */
  539. #define CONFIG_SYS_QE_FW_IN_SPIFLASH
  540. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  541. #elif defined(CONFIG_SDCARD)
  542. /*
  543. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  544. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  545. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  546. */
  547. #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  548. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  549. #elif defined(CONFIG_NAND)
  550. #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  551. #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
  552. #else
  553. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  554. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  555. #endif
  556. #ifdef CONFIG_T1040RDB
  557. #if defined(CONFIG_SPIFLASH)
  558. #define CONFIG_SYS_QE_FW_ADDR 0x130000
  559. #elif defined(CONFIG_SDCARD)
  560. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
  561. #elif defined(CONFIG_NAND)
  562. #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  563. #else
  564. #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
  565. #endif
  566. #endif
  567. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  568. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  569. #endif /* CONFIG_NOBQFMAN */
  570. #ifdef CONFIG_SYS_DPAA_FMAN
  571. #define CONFIG_FMAN_ENET
  572. #define CONFIG_PHY_VITESSE
  573. #define CONFIG_PHY_REALTEK
  574. #endif
  575. #ifdef CONFIG_FMAN_ENET
  576. #ifdef CONFIG_T1040RDB
  577. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
  578. #endif
  579. #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
  580. #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
  581. #define CONFIG_MII /* MII PHY management */
  582. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  583. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  584. #endif
  585. /*
  586. * Environment
  587. */
  588. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  589. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  590. /*
  591. * Command line configuration.
  592. */
  593. #include <config_cmd_default.h>
  594. #ifdef CONFIG_T1042RDB_PI
  595. #define CONFIG_CMD_DATE
  596. #endif
  597. #define CONFIG_CMD_DHCP
  598. #define CONFIG_CMD_ELF
  599. #define CONFIG_CMD_ERRATA
  600. #define CONFIG_CMD_GREPENV
  601. #define CONFIG_CMD_IRQ
  602. #define CONFIG_CMD_I2C
  603. #define CONFIG_CMD_MII
  604. #define CONFIG_CMD_PING
  605. #define CONFIG_CMD_REGINFO
  606. #define CONFIG_CMD_SETEXPR
  607. #ifdef CONFIG_PCI
  608. #define CONFIG_CMD_PCI
  609. #define CONFIG_CMD_NET
  610. #endif
  611. /*
  612. * Miscellaneous configurable options
  613. */
  614. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  615. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  616. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  617. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  618. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  619. #ifdef CONFIG_CMD_KGDB
  620. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  621. #else
  622. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  623. #endif
  624. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  625. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  626. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  627. /*
  628. * For booting Linux, the board info and command line data
  629. * have to be in the first 64 MB of memory, since this is
  630. * the maximum mapped by the Linux kernel during initialization.
  631. */
  632. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  633. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  634. #ifdef CONFIG_CMD_KGDB
  635. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  636. #endif
  637. /*
  638. * Dynamic MTD Partition support with mtdparts
  639. */
  640. #ifndef CONFIG_SYS_NO_FLASH
  641. #define CONFIG_MTD_DEVICE
  642. #define CONFIG_MTD_PARTITIONS
  643. #define CONFIG_CMD_MTDPARTS
  644. #define CONFIG_FLASH_CFI_MTD
  645. #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
  646. "spi0=spife110000.0"
  647. #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
  648. "128k(dtb),96m(fs),-(user);"\
  649. "fff800000.flash:2m(uboot),9m(kernel),"\
  650. "128k(dtb),96m(fs),-(user);spife110000.0:" \
  651. "2m(uboot),9m(kernel),128k(dtb),-(user)"
  652. #endif
  653. /*
  654. * Environment Configuration
  655. */
  656. #define CONFIG_ROOTPATH "/opt/nfsroot"
  657. #define CONFIG_BOOTFILE "uImage"
  658. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  659. /* default location for tftp and bootm */
  660. #define CONFIG_LOADADDR 1000000
  661. #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
  662. #define CONFIG_BAUDRATE 115200
  663. #define __USB_PHY_TYPE utmi
  664. #ifdef CONFIG_T1040RDB
  665. #define FDTFILE "t1040rdb/t1040rdb.dtb"
  666. #define RAMDISKFILE "t1040rdb/ramdisk.uboot"
  667. #elif CONFIG_T1042RDB_PI
  668. #define FDTFILE "t1040rdb_pi/t1040rdb_pi.dtb"
  669. #define RAMDISKFILE "t1040rdb_pi/ramdisk.uboot"
  670. #endif
  671. #define CONFIG_EXTRA_ENV_SETTINGS \
  672. "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
  673. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  674. "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  675. "netdev=eth0\0" \
  676. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  677. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  678. "tftpflash=tftpboot $loadaddr $uboot && " \
  679. "protect off $ubootaddr +$filesize && " \
  680. "erase $ubootaddr +$filesize && " \
  681. "cp.b $loadaddr $ubootaddr $filesize && " \
  682. "protect on $ubootaddr +$filesize && " \
  683. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  684. "consoledev=ttyS0\0" \
  685. "ramdiskaddr=2000000\0" \
  686. "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
  687. "fdtaddr=c00000\0" \
  688. "fdtfile=" __stringify(FDTFILE) "\0" \
  689. "bdev=sda3\0"
  690. #define CONFIG_LINUX \
  691. "setenv bootargs root=/dev/ram rw " \
  692. "console=$consoledev,$baudrate $othbootargs;" \
  693. "setenv ramdiskaddr 0x02000000;" \
  694. "setenv fdtaddr 0x00c00000;" \
  695. "setenv loadaddr 0x1000000;" \
  696. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  697. #define CONFIG_HDBOOT \
  698. "setenv bootargs root=/dev/$bdev rw " \
  699. "console=$consoledev,$baudrate $othbootargs;" \
  700. "tftp $loadaddr $bootfile;" \
  701. "tftp $fdtaddr $fdtfile;" \
  702. "bootm $loadaddr - $fdtaddr"
  703. #define CONFIG_NFSBOOTCOMMAND \
  704. "setenv bootargs root=/dev/nfs rw " \
  705. "nfsroot=$serverip:$rootpath " \
  706. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  707. "console=$consoledev,$baudrate $othbootargs;" \
  708. "tftp $loadaddr $bootfile;" \
  709. "tftp $fdtaddr $fdtfile;" \
  710. "bootm $loadaddr - $fdtaddr"
  711. #define CONFIG_RAMBOOTCOMMAND \
  712. "setenv bootargs root=/dev/ram rw " \
  713. "console=$consoledev,$baudrate $othbootargs;" \
  714. "tftp $ramdiskaddr $ramdiskfile;" \
  715. "tftp $loadaddr $bootfile;" \
  716. "tftp $fdtaddr $fdtfile;" \
  717. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  718. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  719. #ifdef CONFIG_SECURE_BOOT
  720. #include <asm/fsl_secure_boot.h>
  721. #endif
  722. #endif /* __CONFIG_H */