P1_P2_RDB.h 25 KB

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  1. /*
  2. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /*
  7. * P1 P2 RDB board configuration file
  8. * This file is intended to address a set of Low End and Ultra Low End
  9. * Freescale SOCs of QorIQ series(RDB platforms).
  10. * Currently only P2020RDB
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. #ifdef CONFIG_36BIT
  15. #define CONFIG_PHYS_64BIT
  16. #endif
  17. #ifdef CONFIG_P1011RDB
  18. #define CONFIG_P1011
  19. #define CONFIG_SYS_L2_SIZE (256 << 10)
  20. #endif
  21. #ifdef CONFIG_P1020RDB
  22. #define CONFIG_P1020
  23. #define CONFIG_SYS_L2_SIZE (256 << 10)
  24. #endif
  25. #ifdef CONFIG_P2010RDB
  26. #define CONFIG_P2010
  27. #define CONFIG_SYS_L2_SIZE (512 << 10)
  28. #endif
  29. #ifdef CONFIG_P2020RDB
  30. #define CONFIG_P2020
  31. #define CONFIG_SYS_L2_SIZE (512 << 10)
  32. #endif
  33. #ifdef CONFIG_SDCARD
  34. #define CONFIG_SPL 1
  35. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  36. #define CONFIG_SPL_ENV_SUPPORT
  37. #define CONFIG_SPL_SERIAL_SUPPORT
  38. #define CONFIG_SPL_MMC_SUPPORT
  39. #define CONFIG_SPL_MMC_MINIMAL
  40. #define CONFIG_SPL_FLUSH_IMAGE
  41. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  42. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  43. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  44. #define CONFIG_SPL_I2C_SUPPORT
  45. #define CONFIG_SYS_TEXT_BASE 0x11001000
  46. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  47. #define CONFIG_SPL_PAD_TO 0x20000
  48. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  49. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  50. #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
  51. #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
  52. #define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10)
  53. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  54. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  55. #define CONFIG_SPL_MMC_BOOT
  56. #ifdef CONFIG_SPL_BUILD
  57. #define CONFIG_SPL_COMMON_INIT_DDR
  58. #endif
  59. #endif
  60. #ifdef CONFIG_SPIFLASH
  61. #define CONFIG_SPL 1
  62. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  63. #define CONFIG_SPL_ENV_SUPPORT
  64. #define CONFIG_SPL_SERIAL_SUPPORT
  65. #define CONFIG_SPL_SPI_SUPPORT
  66. #define CONFIG_SPL_SPI_FLASH_SUPPORT
  67. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  68. #define CONFIG_SPL_FLUSH_IMAGE
  69. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  70. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  71. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  72. #define CONFIG_SPL_I2C_SUPPORT
  73. #define CONFIG_SYS_TEXT_BASE 0x11001000
  74. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  75. #define CONFIG_SPL_PAD_TO 0x20000
  76. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  77. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  78. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
  79. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
  80. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
  81. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  82. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  83. #define CONFIG_SPL_SPI_BOOT
  84. #ifdef CONFIG_SPL_BUILD
  85. #define CONFIG_SPL_COMMON_INIT_DDR
  86. #endif
  87. #endif
  88. #ifdef CONFIG_NAND
  89. #define CONFIG_SPL 1
  90. #define CONFIG_TPL 1
  91. #ifdef CONFIG_TPL_BUILD
  92. #define CONFIG_SPL_NAND_BOOT
  93. #define CONFIG_SPL_FLUSH_IMAGE
  94. #define CONFIG_SPL_ENV_SUPPORT
  95. #define CONFIG_SPL_NAND_INIT
  96. #define CONFIG_SPL_SERIAL_SUPPORT
  97. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  98. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  99. #define CONFIG_SPL_I2C_SUPPORT
  100. #define CONFIG_SPL_NAND_SUPPORT
  101. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  102. #define CONFIG_SPL_COMMON_INIT_DDR
  103. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  104. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  105. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  106. #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
  107. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  108. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  109. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  110. #elif defined(CONFIG_SPL_BUILD)
  111. #define CONFIG_SPL_INIT_MINIMAL
  112. #define CONFIG_SPL_SERIAL_SUPPORT
  113. #define CONFIG_SPL_NAND_SUPPORT
  114. #define CONFIG_SPL_FLUSH_IMAGE
  115. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  116. #define CONFIG_SPL_TEXT_BASE 0xff800000
  117. #define CONFIG_SPL_MAX_SIZE 4096
  118. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  119. #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
  120. #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
  121. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  122. #endif /* not CONFIG_TPL_BUILD */
  123. #define CONFIG_SPL_PAD_TO 0x20000
  124. #define CONFIG_TPL_PAD_TO 0x20000
  125. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  126. #define CONFIG_SYS_TEXT_BASE 0x11001000
  127. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  128. #endif
  129. #ifndef CONFIG_SYS_TEXT_BASE
  130. #define CONFIG_SYS_TEXT_BASE 0xeff40000
  131. #endif
  132. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  133. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  134. #endif
  135. #ifndef CONFIG_SYS_MONITOR_BASE
  136. #ifdef CONFIG_SPL_BUILD
  137. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  138. #else
  139. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  140. #endif
  141. #endif
  142. /* High Level Configuration Options */
  143. #define CONFIG_BOOKE 1 /* BOOKE */
  144. #define CONFIG_E500 1 /* BOOKE e500 family */
  145. #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
  146. #define CONFIG_PCI 1 /* Enable PCI/PCIE */
  147. #if defined(CONFIG_PCI)
  148. #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
  149. #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
  150. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  151. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  152. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  153. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  154. #endif /* #if defined(CONFIG_PCI) */
  155. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  156. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  157. #define CONFIG_ENV_OVERWRITE
  158. #if defined(CONFIG_PCI)
  159. #define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
  160. #endif
  161. #ifndef __ASSEMBLY__
  162. extern unsigned long get_board_sys_clk(unsigned long dummy);
  163. #endif
  164. #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
  165. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
  166. #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
  167. #define CONFIG_MP
  168. #endif
  169. #define CONFIG_HWCONFIG
  170. /*
  171. * These can be toggled for performance analysis, otherwise use default.
  172. */
  173. #define CONFIG_L2_CACHE /* toggle L2 cache */
  174. #define CONFIG_BTB /* toggle branch predition */
  175. #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
  176. #define CONFIG_ENABLE_36BIT_PHYS 1
  177. #ifdef CONFIG_PHYS_64BIT
  178. #define CONFIG_ADDR_MAP 1
  179. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  180. #endif
  181. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
  182. #define CONFIG_SYS_MEMTEST_END 0x1fffffff
  183. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  184. /*
  185. * Config the L2 Cache as L2 SRAM
  186. */
  187. #if defined(CONFIG_SPL_BUILD)
  188. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  189. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  190. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  191. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  192. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  193. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  194. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
  195. #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
  196. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
  197. #if defined(CONFIG_P2020RDB)
  198. #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
  199. #else
  200. #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
  201. #endif
  202. #elif defined(CONFIG_NAND)
  203. #ifdef CONFIG_TPL_BUILD
  204. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  205. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  206. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  207. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  208. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  209. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  210. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  211. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  212. #else
  213. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  214. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  215. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  216. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
  217. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  218. #endif /* CONFIG_TPL_BUILD */
  219. #endif
  220. #endif
  221. #ifdef CONFIG_SPL_BUILD
  222. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  223. #endif
  224. /* DDR Setup */
  225. #define CONFIG_SYS_FSL_DDR2
  226. #undef CONFIG_FSL_DDR_INTERACTIVE
  227. #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  228. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  229. #if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB)
  230. /*
  231. * P1020 and it's derivatives support max 32bit DDR width
  232. * So Reduce available DDR size
  233. */
  234. #define CONFIG_SYS_SDRAM_SIZE 512
  235. #else
  236. #define CONFIG_SYS_SDRAM_SIZE 1024
  237. #endif
  238. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  239. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  240. #define CONFIG_NUM_DDR_CONTROLLERS 1
  241. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  242. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  243. #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
  244. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  245. #define CONFIG_SYS_DDR_SBE 0x00FF0000
  246. /*
  247. * Memory map
  248. *
  249. * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
  250. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  251. * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  252. *
  253. * Localbus cacheable (TBD)
  254. * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
  255. *
  256. * Localbus non-cacheable
  257. * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
  258. * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
  259. * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
  260. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  261. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  262. */
  263. /*
  264. * Local Bus Definitions
  265. */
  266. #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
  267. #ifdef CONFIG_PHYS_64BIT
  268. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull
  269. #else
  270. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  271. #endif
  272. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  273. BR_PS_16 | BR_V)
  274. #define CONFIG_FLASH_OR_PRELIM 0xff000ff7
  275. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  276. #define CONFIG_SYS_FLASH_QUIET_TEST
  277. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  278. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  279. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  280. #undef CONFIG_SYS_FLASH_CHECKSUM
  281. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  282. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  283. #define CONFIG_FLASH_CFI_DRIVER
  284. #define CONFIG_SYS_FLASH_CFI
  285. #define CONFIG_SYS_FLASH_EMPTY_INFO
  286. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  287. #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  288. #define CONFIG_MISC_INIT_R
  289. #define CONFIG_HWCONFIG
  290. #define CONFIG_SYS_INIT_RAM_LOCK 1
  291. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  292. #ifdef CONFIG_PHYS_64BIT
  293. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  294. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  295. /* The assembler doesn't like typecast */
  296. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  297. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  298. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  299. #else
  300. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
  301. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  302. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  303. #endif
  304. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  305. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
  306. - GENERATED_GBL_DATA_SIZE)
  307. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  308. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  309. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
  310. #define CONFIG_SYS_NAND_BASE 0xff800000
  311. #ifdef CONFIG_PHYS_64BIT
  312. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  313. #else
  314. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  315. #endif
  316. #define CONFIG_CMD_NAND
  317. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  318. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  319. #define CONFIG_MTD_NAND_VERIFY_WRITE
  320. #define CONFIG_NAND_FSL_ELBC 1
  321. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
  322. /* NAND flash config */
  323. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  324. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  325. | BR_PS_8 /* Port Size = 8 bit */ \
  326. | BR_MS_FCM /* MSEL = FCM */ \
  327. | BR_V) /* valid */
  328. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
  329. | OR_FCM_CSCT \
  330. | OR_FCM_CST \
  331. | OR_FCM_CHT \
  332. | OR_FCM_SCY_1 \
  333. | OR_FCM_TRLX \
  334. | OR_FCM_EHTR)
  335. #ifdef CONFIG_NAND
  336. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  337. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  338. #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  339. #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  340. #else
  341. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  342. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  343. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  344. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  345. #endif
  346. #define CONFIG_SYS_VSC7385_BASE 0xffb00000
  347. #ifdef CONFIG_PHYS_64BIT
  348. #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
  349. #else
  350. #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
  351. #endif
  352. #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
  353. | BR_PS_8 | BR_V)
  354. #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
  355. OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
  356. OR_GPCM_EHTR | OR_GPCM_EAD)
  357. /* Serial Port - controlled on board with jumper J8
  358. * open - index 2
  359. * shorted - index 1
  360. */
  361. #define CONFIG_CONS_INDEX 1
  362. #define CONFIG_SYS_NS16550
  363. #define CONFIG_SYS_NS16550_SERIAL
  364. #define CONFIG_SYS_NS16550_REG_SIZE 1
  365. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  366. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  367. #define CONFIG_NS16550_MIN_FUNCTIONS
  368. #endif
  369. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
  370. #define CONFIG_SYS_BAUDRATE_TABLE \
  371. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  372. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  373. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  374. /* Use the HUSH parser */
  375. #define CONFIG_SYS_HUSH_PARSER
  376. /*
  377. * Pass open firmware flat tree
  378. */
  379. #define CONFIG_OF_LIBFDT 1
  380. #define CONFIG_OF_BOARD_SETUP 1
  381. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  382. /* new uImage format support */
  383. #define CONFIG_FIT 1
  384. #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
  385. /* I2C */
  386. #define CONFIG_SYS_I2C
  387. #define CONFIG_SYS_I2C_FSL
  388. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  389. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  390. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  391. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  392. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  393. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  394. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  395. /*
  396. * I2C2 EEPROM
  397. */
  398. #define CONFIG_ID_EEPROM
  399. #ifdef CONFIG_ID_EEPROM
  400. #define CONFIG_SYS_I2C_EEPROM_NXID
  401. #endif
  402. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  403. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  404. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  405. #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
  406. #define CONFIG_RTC_DS1337
  407. #define CONFIG_SYS_RTC_DS1337_NOOSC
  408. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  409. /* eSPI - Enhanced SPI */
  410. #define CONFIG_FSL_ESPI
  411. #define CONFIG_SPI_FLASH
  412. #define CONFIG_SPI_FLASH_SPANSION
  413. #define CONFIG_CMD_SF
  414. #define CONFIG_SF_DEFAULT_SPEED 10000000
  415. #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  416. /*
  417. * General PCI
  418. * Memory space is mapped 1-1, but I/O space must start from 0.
  419. */
  420. #if defined(CONFIG_PCI)
  421. /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  422. #define CONFIG_SYS_PCIE2_NAME "Slot 1"
  423. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  424. #ifdef CONFIG_PHYS_64BIT
  425. #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
  426. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  427. #else
  428. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  429. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  430. #endif
  431. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  432. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  433. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  434. #ifdef CONFIG_PHYS_64BIT
  435. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  436. #else
  437. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  438. #endif
  439. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  440. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  441. #define CONFIG_SYS_PCIE1_NAME "Slot 2"
  442. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  443. #ifdef CONFIG_PHYS_64BIT
  444. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  445. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  446. #else
  447. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  448. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  449. #endif
  450. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  451. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  452. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  453. #ifdef CONFIG_PHYS_64BIT
  454. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
  455. #else
  456. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  457. #endif
  458. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  459. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  460. #undef CONFIG_EEPRO100
  461. #undef CONFIG_TULIP
  462. #undef CONFIG_RTL8139
  463. #ifdef CONFIG_RTL8139
  464. /* This macro is used by RTL8139 but not defined in PPC architecture */
  465. #define KSEG1ADDR(x) (x)
  466. #define _IO_BASE 0x00000000
  467. #endif
  468. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  469. #define CONFIG_DOS_PARTITION
  470. #endif /* CONFIG_PCI */
  471. #if defined(CONFIG_TSEC_ENET)
  472. #define CONFIG_MII 1 /* MII PHY management */
  473. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  474. #define CONFIG_TSEC1 1
  475. #define CONFIG_TSEC1_NAME "eTSEC1"
  476. #define CONFIG_TSEC2 1
  477. #define CONFIG_TSEC2_NAME "eTSEC2"
  478. #define CONFIG_TSEC3 1
  479. #define CONFIG_TSEC3_NAME "eTSEC3"
  480. #define TSEC1_PHY_ADDR 2
  481. #define TSEC2_PHY_ADDR 0
  482. #define TSEC3_PHY_ADDR 1
  483. #define CONFIG_VSC7385_ENET
  484. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  485. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  486. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  487. #define TSEC1_PHYIDX 0
  488. #define TSEC2_PHYIDX 0
  489. #define TSEC3_PHYIDX 0
  490. /* Vitesse 7385 */
  491. #ifdef CONFIG_VSC7385_ENET
  492. /* The size of the VSC7385 firmware image */
  493. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  494. #endif
  495. #define CONFIG_ETHPRIME "eTSEC1"
  496. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  497. #endif /* CONFIG_TSEC_ENET */
  498. /*
  499. * Environment
  500. */
  501. #ifdef CONFIG_SPIFLASH
  502. #define CONFIG_ENV_IS_IN_SPI_FLASH
  503. #define CONFIG_ENV_SPI_BUS 0
  504. #define CONFIG_ENV_SPI_CS 0
  505. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  506. #define CONFIG_ENV_SPI_MODE 0
  507. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  508. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  509. #define CONFIG_ENV_SECT_SIZE 0x10000
  510. #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  511. #elif defined(CONFIG_SDCARD)
  512. #define CONFIG_ENV_IS_IN_MMC
  513. #define CONFIG_FSL_FIXED_MMC_LOCATION
  514. #define CONFIG_ENV_SIZE 0x2000
  515. #define CONFIG_SYS_MMC_ENV_DEV 0
  516. #define CONFIG_ENV_OFFSET (512 * 0x800)
  517. #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  518. #elif defined(CONFIG_NAND)
  519. #ifdef CONFIG_TPL_BUILD
  520. #define CONFIG_ENV_SIZE 0x2000
  521. #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  522. #else
  523. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  524. #endif
  525. #define CONFIG_ENV_IS_IN_NAND
  526. #define CONFIG_ENV_OFFSET (1024 * 1024)
  527. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
  528. #elif defined(CONFIG_SYS_RAMBOOT)
  529. #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
  530. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  531. #define CONFIG_ENV_SIZE 0x2000
  532. #else
  533. #define CONFIG_ENV_IS_IN_FLASH
  534. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  535. #define CONFIG_ENV_SIZE 0x2000
  536. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  537. #endif
  538. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  539. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  540. /*
  541. * Command line configuration.
  542. */
  543. #include <config_cmd_default.h>
  544. #define CONFIG_CMD_DATE
  545. #define CONFIG_CMD_ELF
  546. #define CONFIG_CMD_I2C
  547. #define CONFIG_CMD_IRQ
  548. #define CONFIG_CMD_MII
  549. #define CONFIG_CMD_PING
  550. #define CONFIG_CMD_SETEXPR
  551. #define CONFIG_CMD_REGINFO
  552. #if defined(CONFIG_PCI)
  553. #define CONFIG_CMD_NET
  554. #define CONFIG_CMD_PCI
  555. #endif
  556. #undef CONFIG_WATCHDOG /* watchdog disabled */
  557. #define CONFIG_MMC 1
  558. #ifdef CONFIG_MMC
  559. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  560. #define CONFIG_CMD_MMC
  561. #define CONFIG_DOS_PARTITION
  562. #define CONFIG_FSL_ESDHC
  563. #define CONFIG_GENERIC_MMC
  564. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  565. #ifdef CONFIG_P2020
  566. #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
  567. #endif
  568. #endif
  569. #define CONFIG_HAS_FSL_DR_USB
  570. #if defined(CONFIG_HAS_FSL_DR_USB)
  571. #define CONFIG_USB_EHCI
  572. #ifdef CONFIG_USB_EHCI
  573. #define CONFIG_CMD_USB
  574. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  575. #define CONFIG_USB_EHCI_FSL
  576. #define CONFIG_USB_STORAGE
  577. #endif
  578. #endif
  579. #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
  580. #define CONFIG_CMD_EXT2
  581. #define CONFIG_CMD_FAT
  582. #define CONFIG_DOS_PARTITION
  583. #endif
  584. /*
  585. * Miscellaneous configurable options
  586. */
  587. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  588. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  589. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  590. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  591. #if defined(CONFIG_CMD_KGDB)
  592. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  593. #else
  594. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  595. #endif
  596. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  597. /* Print Buffer Size */
  598. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  599. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  600. /*
  601. * For booting Linux, the board info and command line data
  602. * have to be in the first 64 MB of memory, since this is
  603. * the maximum mapped by the Linux kernel during initialization.
  604. */
  605. #define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/
  606. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  607. #if defined(CONFIG_CMD_KGDB)
  608. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  609. #endif
  610. /*
  611. * Environment Configuration
  612. */
  613. #if defined(CONFIG_TSEC_ENET)
  614. #define CONFIG_HAS_ETH0
  615. #define CONFIG_HAS_ETH1
  616. #define CONFIG_HAS_ETH2
  617. #endif
  618. #define CONFIG_HOSTNAME P2020RDB
  619. #define CONFIG_ROOTPATH "/opt/nfsroot"
  620. #define CONFIG_BOOTFILE "uImage"
  621. #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
  622. /* default location for tftp and bootm */
  623. #define CONFIG_LOADADDR 1000000
  624. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  625. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  626. #define CONFIG_BAUDRATE 115200
  627. #define CONFIG_EXTRA_ENV_SETTINGS \
  628. "netdev=eth0\0" \
  629. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  630. "loadaddr=1000000\0" \
  631. "tftpflash=tftpboot $loadaddr $uboot; " \
  632. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  633. " +$filesize; " \
  634. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  635. " +$filesize; " \
  636. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  637. " $filesize; " \
  638. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  639. " +$filesize; " \
  640. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  641. " $filesize\0" \
  642. "consoledev=ttyS0\0" \
  643. "ramdiskaddr=2000000\0" \
  644. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  645. "fdtaddr=c00000\0" \
  646. "fdtfile=p2020rdb.dtb\0" \
  647. "bdev=sda1\0" \
  648. "jffs2nor=mtdblock3\0" \
  649. "norbootaddr=ef080000\0" \
  650. "norfdtaddr=ef040000\0" \
  651. "jffs2nand=mtdblock9\0" \
  652. "nandbootaddr=100000\0" \
  653. "nandfdtaddr=80000\0" \
  654. "nandimgsize=400000\0" \
  655. "nandfdtsize=80000\0" \
  656. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
  657. "vscfw_addr=ef000000\0" \
  658. "othbootargs=ramdisk_size=600000\0" \
  659. "usbfatboot=setenv bootargs root=/dev/ram rw " \
  660. "console=$consoledev,$baudrate $othbootargs; " \
  661. "usb start;" \
  662. "fatload usb 0:2 $loadaddr $bootfile;" \
  663. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  664. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  665. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  666. "usbext2boot=setenv bootargs root=/dev/ram rw " \
  667. "console=$consoledev,$baudrate $othbootargs; " \
  668. "usb start;" \
  669. "ext2load usb 0:4 $loadaddr $bootfile;" \
  670. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  671. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  672. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  673. "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
  674. "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
  675. "bootm $norbootaddr - $norfdtaddr\0" \
  676. "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
  677. "console=$consoledev,$baudrate $othbootargs;" \
  678. "nand read 2000000 $nandbootaddr $nandimgsize;" \
  679. "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
  680. "bootm 2000000 - 3000000;\0"
  681. #define CONFIG_NFSBOOTCOMMAND \
  682. "setenv bootargs root=/dev/nfs rw " \
  683. "nfsroot=$serverip:$rootpath " \
  684. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  685. "console=$consoledev,$baudrate $othbootargs;" \
  686. "tftp $loadaddr $bootfile;" \
  687. "tftp $fdtaddr $fdtfile;" \
  688. "bootm $loadaddr - $fdtaddr"
  689. #define CONFIG_HDBOOT \
  690. "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  691. "console=$consoledev,$baudrate $othbootargs;" \
  692. "usb start;" \
  693. "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  694. "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  695. "bootm $loadaddr - $fdtaddr"
  696. #define CONFIG_RAMBOOTCOMMAND \
  697. "setenv bootargs root=/dev/ram rw " \
  698. "console=$consoledev,$baudrate $othbootargs; " \
  699. "tftp $ramdiskaddr $ramdiskfile;" \
  700. "tftp $loadaddr $bootfile;" \
  701. "tftp $fdtaddr $fdtfile;" \
  702. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  703. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  704. #endif /* __CONFIG_H */