P1022DS.h 24 KB

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  1. /*
  2. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  3. * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  4. * Timur Tabi <timur@freescale.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include "../board/freescale/common/ics307_clk.h"
  11. #ifdef CONFIG_36BIT
  12. #define CONFIG_PHYS_64BIT
  13. #endif
  14. #ifdef CONFIG_SDCARD
  15. #define CONFIG_SPL 1
  16. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  17. #define CONFIG_SPL_ENV_SUPPORT
  18. #define CONFIG_SPL_SERIAL_SUPPORT
  19. #define CONFIG_SPL_MMC_SUPPORT
  20. #define CONFIG_SPL_MMC_MINIMAL
  21. #define CONFIG_SPL_FLUSH_IMAGE
  22. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  23. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  24. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  25. #define CONFIG_SPL_I2C_SUPPORT
  26. #define CONFIG_FSL_LAW /* Use common FSL init code */
  27. #define CONFIG_SYS_TEXT_BASE 0x11001000
  28. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  29. #define CONFIG_SPL_PAD_TO 0x20000
  30. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  31. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  32. #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
  33. #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
  34. #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
  35. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  36. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  37. #define CONFIG_SPL_MMC_BOOT
  38. #ifdef CONFIG_SPL_BUILD
  39. #define CONFIG_SPL_COMMON_INIT_DDR
  40. #endif
  41. #endif
  42. #ifdef CONFIG_SPIFLASH
  43. #define CONFIG_SPL 1
  44. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  45. #define CONFIG_SPL_ENV_SUPPORT
  46. #define CONFIG_SPL_SERIAL_SUPPORT
  47. #define CONFIG_SPL_SPI_SUPPORT
  48. #define CONFIG_SPL_SPI_FLASH_SUPPORT
  49. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  50. #define CONFIG_SPL_FLUSH_IMAGE
  51. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  52. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  53. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  54. #define CONFIG_SPL_I2C_SUPPORT
  55. #define CONFIG_FSL_LAW /* Use common FSL init code */
  56. #define CONFIG_SYS_TEXT_BASE 0x11001000
  57. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  58. #define CONFIG_SPL_PAD_TO 0x20000
  59. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  60. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  61. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
  62. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
  63. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
  64. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  65. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  66. #define CONFIG_SPL_SPI_BOOT
  67. #ifdef CONFIG_SPL_BUILD
  68. #define CONFIG_SPL_COMMON_INIT_DDR
  69. #endif
  70. #endif
  71. #define CONFIG_NAND_FSL_ELBC
  72. #define CONFIG_SYS_NAND_MAX_ECCPOS 56
  73. #define CONFIG_SYS_NAND_MAX_OOBFREE 5
  74. #ifdef CONFIG_NAND
  75. #define CONFIG_SPL 1
  76. #define CONFIG_TPL 1
  77. #ifdef CONFIG_TPL_BUILD
  78. #define CONFIG_SPL_NAND_BOOT
  79. #define CONFIG_SPL_FLUSH_IMAGE
  80. #define CONFIG_SPL_ENV_SUPPORT
  81. #define CONFIG_SPL_NAND_INIT
  82. #define CONFIG_SPL_SERIAL_SUPPORT
  83. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  84. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  85. #define CONFIG_SPL_I2C_SUPPORT
  86. #define CONFIG_SPL_NAND_SUPPORT
  87. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  88. #define CONFIG_SPL_COMMON_INIT_DDR
  89. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  90. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  91. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  92. #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
  93. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  94. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  95. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  96. #elif defined(CONFIG_SPL_BUILD)
  97. #define CONFIG_SPL_INIT_MINIMAL
  98. #define CONFIG_SPL_SERIAL_SUPPORT
  99. #define CONFIG_SPL_NAND_SUPPORT
  100. #define CONFIG_SPL_FLUSH_IMAGE
  101. #define CONFIG_SPL_TEXT_BASE 0xff800000
  102. #define CONFIG_SPL_MAX_SIZE 4096
  103. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  104. #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
  105. #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
  106. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  107. #endif
  108. #define CONFIG_SPL_PAD_TO 0x20000
  109. #define CONFIG_TPL_PAD_TO 0x20000
  110. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  111. #define CONFIG_SYS_TEXT_BASE 0x11001000
  112. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  113. #endif
  114. /* High Level Configuration Options */
  115. #define CONFIG_BOOKE /* BOOKE */
  116. #define CONFIG_E500 /* BOOKE e500 family */
  117. #define CONFIG_P1022
  118. #define CONFIG_P1022DS
  119. #define CONFIG_MP /* support multiple processors */
  120. #ifndef CONFIG_SYS_TEXT_BASE
  121. #define CONFIG_SYS_TEXT_BASE 0xeff40000
  122. #endif
  123. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  124. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  125. #endif
  126. #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
  127. #define CONFIG_PCI /* Enable PCI/PCIE */
  128. #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
  129. #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
  130. #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
  131. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  132. #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  133. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  134. #define CONFIG_ENABLE_36BIT_PHYS
  135. #ifdef CONFIG_PHYS_64BIT
  136. #define CONFIG_ADDR_MAP
  137. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  138. #endif
  139. #define CONFIG_FSL_LAW /* Use common FSL init code */
  140. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  141. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  142. #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
  143. /*
  144. * These can be toggled for performance analysis, otherwise use default.
  145. */
  146. #define CONFIG_L2_CACHE
  147. #define CONFIG_BTB
  148. #define CONFIG_SYS_MEMTEST_START 0x00000000
  149. #define CONFIG_SYS_MEMTEST_END 0x7fffffff
  150. #define CONFIG_SYS_CCSRBAR 0xffe00000
  151. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  152. /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
  153. SPL code*/
  154. #ifdef CONFIG_SPL_BUILD
  155. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  156. #endif
  157. /* DDR Setup */
  158. #define CONFIG_DDR_SPD
  159. #define CONFIG_VERY_BIG_RAM
  160. #define CONFIG_SYS_FSL_DDR3
  161. #ifdef CONFIG_DDR_ECC
  162. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  163. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  164. #endif
  165. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  166. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  167. #define CONFIG_NUM_DDR_CONTROLLERS 1
  168. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  169. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  170. /* I2C addresses of SPD EEPROMs */
  171. #define CONFIG_SYS_SPD_BUS_NUM 1
  172. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  173. /* These are used when DDR doesn't use SPD. */
  174. #define CONFIG_SYS_SDRAM_SIZE 2048
  175. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
  176. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
  177. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
  178. #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
  179. #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
  180. #define CONFIG_SYS_DDR_TIMING_3 0x00010000
  181. #define CONFIG_SYS_DDR_TIMING_0 0x40110104
  182. #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
  183. #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
  184. #define CONFIG_SYS_DDR_MODE_1 0x00441221
  185. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  186. #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
  187. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  188. #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
  189. #define CONFIG_SYS_DDR_CONTROL 0xc7000008
  190. #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
  191. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  192. #define CONFIG_SYS_DDR_TIMING_5 0x02401400
  193. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  194. #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
  195. /*
  196. * Memory map
  197. *
  198. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  199. * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
  200. * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
  201. *
  202. * Localbus cacheable (TBD)
  203. * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
  204. *
  205. * Localbus non-cacheable
  206. * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
  207. * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
  208. * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
  209. * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
  210. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  211. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  212. */
  213. /*
  214. * Local Bus Definitions
  215. */
  216. #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
  217. #ifdef CONFIG_PHYS_64BIT
  218. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
  219. #else
  220. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  221. #endif
  222. #define CONFIG_FLASH_BR_PRELIM \
  223. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  224. #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
  225. #ifdef CONFIG_NAND
  226. #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  227. #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  228. #else
  229. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  230. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  231. #endif
  232. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  233. #define CONFIG_SYS_FLASH_QUIET_TEST
  234. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  235. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  236. #define CONFIG_SYS_MAX_FLASH_SECT 1024
  237. #ifndef CONFIG_SYS_MONITOR_BASE
  238. #ifdef CONFIG_SPL_BUILD
  239. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  240. #else
  241. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  242. #endif
  243. #endif
  244. #define CONFIG_FLASH_CFI_DRIVER
  245. #define CONFIG_SYS_FLASH_CFI
  246. #define CONFIG_SYS_FLASH_EMPTY_INFO
  247. /* Nand Flash */
  248. #if defined(CONFIG_NAND_FSL_ELBC)
  249. #define CONFIG_SYS_NAND_BASE 0xff800000
  250. #ifdef CONFIG_PHYS_64BIT
  251. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  252. #else
  253. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  254. #endif
  255. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  256. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  257. #define CONFIG_MTD_NAND_VERIFY_WRITE
  258. #define CONFIG_CMD_NAND 1
  259. #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
  260. #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
  261. /* NAND flash config */
  262. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  263. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  264. | BR_PS_8 /* Port Size = 8 bit */ \
  265. | BR_MS_FCM /* MSEL = FCM */ \
  266. | BR_V) /* valid */
  267. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
  268. | OR_FCM_PGS /* Large Page*/ \
  269. | OR_FCM_CSCT \
  270. | OR_FCM_CST \
  271. | OR_FCM_CHT \
  272. | OR_FCM_SCY_1 \
  273. | OR_FCM_TRLX \
  274. | OR_FCM_EHTR)
  275. #ifdef CONFIG_NAND
  276. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  277. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  278. #else
  279. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  280. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  281. #endif
  282. #endif /* CONFIG_NAND_FSL_ELBC */
  283. #define CONFIG_BOARD_EARLY_INIT_F
  284. #define CONFIG_BOARD_EARLY_INIT_R
  285. #define CONFIG_MISC_INIT_R
  286. #define CONFIG_HWCONFIG
  287. #define CONFIG_FSL_NGPIXIS
  288. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  289. #ifdef CONFIG_PHYS_64BIT
  290. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  291. #else
  292. #define PIXIS_BASE_PHYS PIXIS_BASE
  293. #endif
  294. #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  295. #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
  296. #define PIXIS_LBMAP_SWITCH 7
  297. #define PIXIS_LBMAP_MASK 0xF0
  298. #define PIXIS_LBMAP_ALTBANK 0x20
  299. #define PIXIS_SPD 0x07
  300. #define PIXIS_SPD_SYSCLK_MASK 0x07
  301. #define PIXIS_ELBC_SPI_MASK 0xc0
  302. #define PIXIS_SPI 0x80
  303. #define CONFIG_SYS_INIT_RAM_LOCK
  304. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  305. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  306. #define CONFIG_SYS_GBL_DATA_OFFSET \
  307. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  308. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  309. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  310. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  311. /*
  312. * Config the L2 Cache as L2 SRAM
  313. */
  314. #if defined(CONFIG_SPL_BUILD)
  315. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  316. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  317. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  318. #define CONFIG_SYS_L2_SIZE (256 << 10)
  319. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  320. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  321. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
  322. #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
  323. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
  324. #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
  325. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  326. #elif defined(CONFIG_NAND)
  327. #ifdef CONFIG_TPL_BUILD
  328. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  329. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  330. #define CONFIG_SYS_L2_SIZE (256 << 10)
  331. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  332. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  333. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  334. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  335. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  336. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  337. #else
  338. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  339. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  340. #define CONFIG_SYS_L2_SIZE (256 << 10)
  341. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  342. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
  343. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  344. #endif
  345. #endif
  346. #endif
  347. /*
  348. * Serial Port
  349. */
  350. #define CONFIG_CONS_INDEX 1
  351. #define CONFIG_SYS_NS16550
  352. #define CONFIG_SYS_NS16550_SERIAL
  353. #define CONFIG_SYS_NS16550_REG_SIZE 1
  354. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  355. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  356. #define CONFIG_NS16550_MIN_FUNCTIONS
  357. #endif
  358. #define CONFIG_SYS_BAUDRATE_TABLE \
  359. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  360. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  361. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  362. /* Use the HUSH parser */
  363. #define CONFIG_SYS_HUSH_PARSER
  364. /* Video */
  365. #ifdef CONFIG_FSL_DIU_FB
  366. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
  367. #define CONFIG_VIDEO
  368. #define CONFIG_CMD_BMP
  369. #define CONFIG_CFB_CONSOLE
  370. #define CONFIG_VIDEO_SW_CURSOR
  371. #define CONFIG_VGA_AS_SINGLE_DEVICE
  372. #define CONFIG_VIDEO_LOGO
  373. #define CONFIG_VIDEO_BMP_LOGO
  374. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  375. /*
  376. * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  377. * disable empty flash sector detection, which is I/O-intensive.
  378. */
  379. #undef CONFIG_SYS_FLASH_EMPTY_INFO
  380. #endif
  381. #ifndef CONFIG_FSL_DIU_FB
  382. #endif
  383. #ifdef CONFIG_ATI
  384. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
  385. #define CONFIG_VIDEO
  386. #define CONFIG_BIOSEMU
  387. #define CONFIG_VIDEO_SW_CURSOR
  388. #define CONFIG_ATI_RADEON_FB
  389. #define CONFIG_VIDEO_LOGO
  390. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
  391. #define CONFIG_CFB_CONSOLE
  392. #define CONFIG_VGA_AS_SINGLE_DEVICE
  393. #endif
  394. /*
  395. * Pass open firmware flat tree
  396. */
  397. #define CONFIG_OF_LIBFDT
  398. #define CONFIG_OF_BOARD_SETUP
  399. #define CONFIG_OF_STDOUT_VIA_ALIAS
  400. /* new uImage format support */
  401. #define CONFIG_FIT
  402. #define CONFIG_FIT_VERBOSE
  403. /* I2C */
  404. #define CONFIG_SYS_I2C
  405. #define CONFIG_SYS_I2C_FSL
  406. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  407. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  408. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  409. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  410. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  411. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  412. #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
  413. /*
  414. * I2C2 EEPROM
  415. */
  416. #define CONFIG_ID_EEPROM
  417. #define CONFIG_SYS_I2C_EEPROM_NXID
  418. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  419. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  420. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  421. /*
  422. * eSPI - Enhanced SPI
  423. */
  424. #define CONFIG_SPI_FLASH
  425. #define CONFIG_SPI_FLASH_SPANSION
  426. #define CONFIG_HARD_SPI
  427. #define CONFIG_FSL_ESPI
  428. #define CONFIG_CMD_SF
  429. #define CONFIG_SF_DEFAULT_SPEED 10000000
  430. #define CONFIG_SF_DEFAULT_MODE 0
  431. /*
  432. * General PCI
  433. * Memory space is mapped 1-1, but I/O space must start from 0.
  434. */
  435. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  436. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  437. #ifdef CONFIG_PHYS_64BIT
  438. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  439. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
  440. #else
  441. #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
  442. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
  443. #endif
  444. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  445. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
  446. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  447. #ifdef CONFIG_PHYS_64BIT
  448. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
  449. #else
  450. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
  451. #endif
  452. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  453. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  454. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  455. #ifdef CONFIG_PHYS_64BIT
  456. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  457. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  458. #else
  459. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  460. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  461. #endif
  462. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  463. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  464. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  465. #ifdef CONFIG_PHYS_64BIT
  466. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  467. #else
  468. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  469. #endif
  470. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  471. /* controller 3, Slot 1, tgtid 3, Base address b000 */
  472. #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
  473. #ifdef CONFIG_PHYS_64BIT
  474. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  475. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
  476. #else
  477. #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
  478. #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
  479. #endif
  480. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  481. #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
  482. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  483. #ifdef CONFIG_PHYS_64BIT
  484. #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
  485. #else
  486. #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
  487. #endif
  488. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  489. #ifdef CONFIG_PCI
  490. #define CONFIG_PCI_INDIRECT_BRIDGE
  491. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  492. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  493. #define CONFIG_E1000 /* Define e1000 pci Ethernet card */
  494. #endif
  495. /* SATA */
  496. #define CONFIG_LIBATA
  497. #define CONFIG_FSL_SATA
  498. #define CONFIG_FSL_SATA_V2
  499. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  500. #define CONFIG_SATA1
  501. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  502. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  503. #define CONFIG_SATA2
  504. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  505. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  506. #ifdef CONFIG_FSL_SATA
  507. #define CONFIG_LBA48
  508. #define CONFIG_CMD_SATA
  509. #define CONFIG_DOS_PARTITION
  510. #define CONFIG_CMD_EXT2
  511. #endif
  512. #define CONFIG_MMC
  513. #ifdef CONFIG_MMC
  514. #define CONFIG_CMD_MMC
  515. #define CONFIG_FSL_ESDHC
  516. #define CONFIG_GENERIC_MMC
  517. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  518. #endif
  519. #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
  520. #define CONFIG_CMD_EXT2
  521. #define CONFIG_CMD_FAT
  522. #define CONFIG_DOS_PARTITION
  523. #endif
  524. #define CONFIG_TSEC_ENET
  525. #ifdef CONFIG_TSEC_ENET
  526. #define CONFIG_TSECV2
  527. #define CONFIG_MII /* MII PHY management */
  528. #define CONFIG_TSEC1 1
  529. #define CONFIG_TSEC1_NAME "eTSEC1"
  530. #define CONFIG_TSEC2 1
  531. #define CONFIG_TSEC2_NAME "eTSEC2"
  532. #define TSEC1_PHY_ADDR 1
  533. #define TSEC2_PHY_ADDR 2
  534. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  535. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  536. #define TSEC1_PHYIDX 0
  537. #define TSEC2_PHYIDX 0
  538. #define CONFIG_ETHPRIME "eTSEC1"
  539. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  540. #endif
  541. /*
  542. * Environment
  543. */
  544. #ifdef CONFIG_SPIFLASH
  545. #define CONFIG_ENV_IS_IN_SPI_FLASH
  546. #define CONFIG_ENV_SPI_BUS 0
  547. #define CONFIG_ENV_SPI_CS 0
  548. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  549. #define CONFIG_ENV_SPI_MODE 0
  550. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  551. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  552. #define CONFIG_ENV_SECT_SIZE 0x10000
  553. #elif defined(CONFIG_SDCARD)
  554. #define CONFIG_ENV_IS_IN_MMC
  555. #define CONFIG_FSL_FIXED_MMC_LOCATION
  556. #define CONFIG_ENV_SIZE 0x2000
  557. #define CONFIG_SYS_MMC_ENV_DEV 0
  558. #elif defined(CONFIG_NAND)
  559. #ifdef CONFIG_TPL_BUILD
  560. #define CONFIG_ENV_SIZE 0x2000
  561. #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  562. #else
  563. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  564. #endif
  565. #define CONFIG_ENV_IS_IN_NAND
  566. #define CONFIG_ENV_OFFSET (1024 * 1024)
  567. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
  568. #elif defined(CONFIG_SYS_RAMBOOT)
  569. #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
  570. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  571. #define CONFIG_ENV_SIZE 0x2000
  572. #else
  573. #define CONFIG_ENV_IS_IN_FLASH
  574. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  575. #define CONFIG_ENV_SIZE 0x2000
  576. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  577. #endif
  578. #define CONFIG_LOADS_ECHO
  579. #define CONFIG_SYS_LOADS_BAUD_CHANGE
  580. /*
  581. * Command line configuration.
  582. */
  583. #include <config_cmd_default.h>
  584. #define CONFIG_CMD_ELF
  585. #define CONFIG_CMD_ERRATA
  586. #define CONFIG_CMD_IRQ
  587. #define CONFIG_CMD_I2C
  588. #define CONFIG_CMD_MII
  589. #define CONFIG_CMD_PING
  590. #define CONFIG_CMD_SETEXPR
  591. #define CONFIG_CMD_REGINFO
  592. #ifdef CONFIG_PCI
  593. #define CONFIG_CMD_PCI
  594. #define CONFIG_CMD_NET
  595. #endif
  596. /*
  597. * USB
  598. */
  599. #define CONFIG_HAS_FSL_DR_USB
  600. #ifdef CONFIG_HAS_FSL_DR_USB
  601. #define CONFIG_USB_EHCI
  602. #ifdef CONFIG_USB_EHCI
  603. #define CONFIG_CMD_USB
  604. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  605. #define CONFIG_USB_EHCI_FSL
  606. #define CONFIG_USB_STORAGE
  607. #define CONFIG_CMD_FAT
  608. #endif
  609. #endif
  610. /*
  611. * Miscellaneous configurable options
  612. */
  613. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  614. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  615. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  616. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  617. #ifdef CONFIG_CMD_KGDB
  618. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  619. #else
  620. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  621. #endif
  622. /* Print Buffer Size */
  623. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  624. #define CONFIG_SYS_MAXARGS 16
  625. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  626. /*
  627. * For booting Linux, the board info and command line data
  628. * have to be in the first 64 MB of memory, since this is
  629. * the maximum mapped by the Linux kernel during initialization.
  630. */
  631. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  632. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  633. #ifdef CONFIG_CMD_KGDB
  634. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  635. #endif
  636. /*
  637. * Environment Configuration
  638. */
  639. #define CONFIG_HOSTNAME p1022ds
  640. #define CONFIG_ROOTPATH "/opt/nfsroot"
  641. #define CONFIG_BOOTFILE "uImage"
  642. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  643. #define CONFIG_LOADADDR 1000000
  644. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  645. #define CONFIG_BAUDRATE 115200
  646. #define CONFIG_EXTRA_ENV_SETTINGS \
  647. "netdev=eth0\0" \
  648. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  649. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  650. "tftpflash=tftpboot $loadaddr $uboot && " \
  651. "protect off $ubootaddr +$filesize && " \
  652. "erase $ubootaddr +$filesize && " \
  653. "cp.b $loadaddr $ubootaddr $filesize && " \
  654. "protect on $ubootaddr +$filesize && " \
  655. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  656. "consoledev=ttyS0\0" \
  657. "ramdiskaddr=2000000\0" \
  658. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  659. "fdtaddr=c00000\0" \
  660. "fdtfile=p1022ds.dtb\0" \
  661. "bdev=sda3\0" \
  662. "hwconfig=esdhc;audclk:12\0"
  663. #define CONFIG_HDBOOT \
  664. "setenv bootargs root=/dev/$bdev rw " \
  665. "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
  666. "tftp $loadaddr $bootfile;" \
  667. "tftp $fdtaddr $fdtfile;" \
  668. "bootm $loadaddr - $fdtaddr"
  669. #define CONFIG_NFSBOOTCOMMAND \
  670. "setenv bootargs root=/dev/nfs rw " \
  671. "nfsroot=$serverip:$rootpath " \
  672. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  673. "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
  674. "tftp $loadaddr $bootfile;" \
  675. "tftp $fdtaddr $fdtfile;" \
  676. "bootm $loadaddr - $fdtaddr"
  677. #define CONFIG_RAMBOOTCOMMAND \
  678. "setenv bootargs root=/dev/ram rw " \
  679. "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
  680. "tftp $ramdiskaddr $ramdiskfile;" \
  681. "tftp $loadaddr $bootfile;" \
  682. "tftp $fdtaddr $fdtfile;" \
  683. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  684. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  685. #endif