P1010RDB.h 31 KB

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  1. /*
  2. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /*
  7. * P010 RDB board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #ifdef CONFIG_36BIT
  12. #define CONFIG_PHYS_64BIT
  13. #endif
  14. #define CONFIG_P1010
  15. #define CONFIG_E500 /* BOOKE e500 family */
  16. #include <asm/config_mpc85xx.h>
  17. #define CONFIG_NAND_FSL_IFC
  18. #ifdef CONFIG_SDCARD
  19. #define CONFIG_SPL 1
  20. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  21. #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  22. #define CONFIG_SPL_ENV_SUPPORT
  23. #define CONFIG_SPL_SERIAL_SUPPORT
  24. #define CONFIG_SPL_MMC_SUPPORT
  25. #define CONFIG_SPL_MMC_MINIMAL
  26. #define CONFIG_SPL_FLUSH_IMAGE
  27. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  28. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  29. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  30. #define CONFIG_SPL_I2C_SUPPORT
  31. #define CONFIG_FSL_LAW /* Use common FSL init code */
  32. #define CONFIG_SYS_TEXT_BASE 0x11001000
  33. #define CONFIG_SPL_TEXT_BASE 0xD0001000
  34. #define CONFIG_SPL_PAD_TO 0x18000
  35. #define CONFIG_SPL_MAX_SIZE (96 * 1024)
  36. #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
  37. #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
  38. #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
  39. #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
  40. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  41. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  42. #define CONFIG_SPL_MMC_BOOT
  43. #ifdef CONFIG_SPL_BUILD
  44. #define CONFIG_SPL_COMMON_INIT_DDR
  45. #endif
  46. #endif
  47. #ifdef CONFIG_SPIFLASH
  48. #ifdef CONFIG_SECURE_BOOT
  49. #define CONFIG_RAMBOOT_SPIFLASH
  50. #define CONFIG_SYS_TEXT_BASE 0x11000000
  51. #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
  52. #else
  53. #define CONFIG_SPL 1
  54. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  55. #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  56. #define CONFIG_SPL_ENV_SUPPORT
  57. #define CONFIG_SPL_SERIAL_SUPPORT
  58. #define CONFIG_SPL_SPI_SUPPORT
  59. #define CONFIG_SPL_SPI_FLASH_SUPPORT
  60. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  61. #define CONFIG_SPL_FLUSH_IMAGE
  62. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  63. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  64. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  65. #define CONFIG_SPL_I2C_SUPPORT
  66. #define CONFIG_FSL_LAW /* Use common FSL init code */
  67. #define CONFIG_SYS_TEXT_BASE 0x11001000
  68. #define CONFIG_SPL_TEXT_BASE 0xD0001000
  69. #define CONFIG_SPL_PAD_TO 0x18000
  70. #define CONFIG_SPL_MAX_SIZE (96 * 1024)
  71. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
  72. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
  73. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
  74. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
  75. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  76. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  77. #define CONFIG_SPL_SPI_BOOT
  78. #ifdef CONFIG_SPL_BUILD
  79. #define CONFIG_SPL_COMMON_INIT_DDR
  80. #endif
  81. #endif
  82. #endif
  83. #ifdef CONFIG_NAND
  84. #define CONFIG_SPL 1
  85. #ifdef CONFIG_SECURE_BOOT
  86. #define CONFIG_SPL_INIT_MINIMAL
  87. #define CONFIG_SPL_SERIAL_SUPPORT
  88. #define CONFIG_SPL_NAND_SUPPORT
  89. #define CONFIG_SPL_NAND_BOOT
  90. #define CONFIG_SPL_FLUSH_IMAGE
  91. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  92. #define CONFIG_SYS_TEXT_BASE 0x00201000
  93. #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
  94. #define CONFIG_SPL_MAX_SIZE 8192
  95. #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
  96. #define CONFIG_SPL_RELOC_STACK 0x00100000
  97. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
  98. #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
  99. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  100. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
  101. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  102. #else
  103. #define CONFIG_TPL 1
  104. #ifdef CONFIG_TPL_BUILD
  105. #define CONFIG_SPL_NAND_BOOT
  106. #define CONFIG_SPL_FLUSH_IMAGE
  107. #define CONFIG_SPL_ENV_SUPPORT
  108. #define CONFIG_SPL_NAND_INIT
  109. #define CONFIG_SPL_SERIAL_SUPPORT
  110. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  111. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  112. #define CONFIG_SPL_I2C_SUPPORT
  113. #define CONFIG_SPL_NAND_SUPPORT
  114. #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  115. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  116. #define CONFIG_SPL_COMMON_INIT_DDR
  117. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  118. #define CONFIG_SPL_TEXT_BASE 0xD0001000
  119. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  120. #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
  121. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  122. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  123. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  124. #elif defined(CONFIG_SPL_BUILD)
  125. #define CONFIG_SPL_INIT_MINIMAL
  126. #define CONFIG_SPL_SERIAL_SUPPORT
  127. #define CONFIG_SPL_NAND_SUPPORT
  128. #define CONFIG_SPL_NAND_MINIMAL
  129. #define CONFIG_SPL_FLUSH_IMAGE
  130. #define CONFIG_SPL_TEXT_BASE 0xff800000
  131. #define CONFIG_SPL_MAX_SIZE 8192
  132. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  133. #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
  134. #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
  135. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  136. #endif
  137. #define CONFIG_SPL_PAD_TO 0x20000
  138. #define CONFIG_TPL_PAD_TO 0x20000
  139. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  140. #define CONFIG_SYS_TEXT_BASE 0x11001000
  141. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  142. #endif
  143. #endif
  144. #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
  145. #define CONFIG_RAMBOOT_NAND
  146. #define CONFIG_SYS_TEXT_BASE 0x11000000
  147. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  148. #endif
  149. #ifndef CONFIG_SYS_TEXT_BASE
  150. #define CONFIG_SYS_TEXT_BASE 0xeff40000
  151. #endif
  152. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  153. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  154. #endif
  155. #ifdef CONFIG_SPL_BUILD
  156. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  157. #else
  158. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  159. #endif
  160. /* High Level Configuration Options */
  161. #define CONFIG_BOOKE /* BOOKE */
  162. #define CONFIG_E500 /* BOOKE e500 family */
  163. #define CONFIG_FSL_IFC /* Enable IFC Support */
  164. #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
  165. #define CONFIG_PCI /* Enable PCI/PCIE */
  166. #if defined(CONFIG_PCI)
  167. #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
  168. #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
  169. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  170. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  171. #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  172. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  173. #define CONFIG_CMD_NET
  174. #define CONFIG_CMD_PCI
  175. #define CONFIG_E1000 /* E1000 pci Ethernet card*/
  176. /*
  177. * PCI Windows
  178. * Memory space is mapped 1-1, but I/O space must start from 0.
  179. */
  180. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  181. #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
  182. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  183. #ifdef CONFIG_PHYS_64BIT
  184. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  185. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  186. #else
  187. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  188. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  189. #endif
  190. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  191. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  192. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  193. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  194. #ifdef CONFIG_PHYS_64BIT
  195. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
  196. #else
  197. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  198. #endif
  199. /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  200. #if defined(CONFIG_P1010RDB_PA)
  201. #define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
  202. #elif defined(CONFIG_P1010RDB_PB)
  203. #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
  204. #endif
  205. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  206. #ifdef CONFIG_PHYS_64BIT
  207. #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
  208. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  209. #else
  210. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  211. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  212. #endif
  213. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  214. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  215. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  216. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  217. #ifdef CONFIG_PHYS_64BIT
  218. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  219. #else
  220. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  221. #endif
  222. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  223. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  224. #define CONFIG_DOS_PARTITION
  225. #endif
  226. #define CONFIG_FSL_LAW /* Use common FSL init code */
  227. #define CONFIG_TSEC_ENET
  228. #define CONFIG_ENV_OVERWRITE
  229. #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
  230. #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
  231. #define CONFIG_MISC_INIT_R
  232. #define CONFIG_HWCONFIG
  233. /*
  234. * These can be toggled for performance analysis, otherwise use default.
  235. */
  236. #define CONFIG_L2_CACHE /* toggle L2 cache */
  237. #define CONFIG_BTB /* toggle branch predition */
  238. #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
  239. #define CONFIG_ENABLE_36BIT_PHYS
  240. #ifdef CONFIG_PHYS_64BIT
  241. #define CONFIG_ADDR_MAP 1
  242. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  243. #endif
  244. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  245. #define CONFIG_SYS_MEMTEST_END 0x1fffffff
  246. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  247. /* DDR Setup */
  248. #define CONFIG_SYS_FSL_DDR3
  249. #define CONFIG_SYS_DDR_RAW_TIMING
  250. #define CONFIG_DDR_SPD
  251. #define CONFIG_SYS_SPD_BUS_NUM 1
  252. #define SPD_EEPROM_ADDRESS 0x52
  253. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  254. #ifndef __ASSEMBLY__
  255. extern unsigned long get_sdram_size(void);
  256. #endif
  257. #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
  258. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  259. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  260. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  261. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  262. /* DDR3 Controller Settings */
  263. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  264. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  265. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  266. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  267. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  268. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  269. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  270. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  271. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  272. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  273. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  274. #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
  275. #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
  276. #define CONFIG_SYS_DDR_TIMING_4 0x00000001
  277. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  278. #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
  279. #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
  280. #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
  281. #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
  282. #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
  283. #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
  284. #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
  285. #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
  286. #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
  287. /* settings for DDR3 at 667MT/s */
  288. #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
  289. #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
  290. #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
  291. #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
  292. #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
  293. #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
  294. #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
  295. #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
  296. #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
  297. #define CONFIG_SYS_CCSRBAR 0xffe00000
  298. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  299. /* Don't relocate CCSRBAR while in NAND_SPL */
  300. #ifdef CONFIG_SPL_BUILD
  301. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  302. #endif
  303. /*
  304. * Memory map
  305. *
  306. * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
  307. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
  308. * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  309. *
  310. * Localbus non-cacheable
  311. * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
  312. * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
  313. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  314. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  315. */
  316. /*
  317. * IFC Definitions
  318. */
  319. /* NOR Flash on IFC */
  320. #ifdef CONFIG_SPL_BUILD
  321. #define CONFIG_SYS_NO_FLASH
  322. #endif
  323. #define CONFIG_SYS_FLASH_BASE 0xee000000
  324. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
  325. #ifdef CONFIG_PHYS_64BIT
  326. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  327. #else
  328. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  329. #endif
  330. #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  331. CSPR_PORT_SIZE_16 | \
  332. CSPR_MSEL_NOR | \
  333. CSPR_V)
  334. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
  335. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
  336. /* NOR Flash Timing Params */
  337. #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
  338. FTIM0_NOR_TEADC(0x5) | \
  339. FTIM0_NOR_TEAHC(0x5)
  340. #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
  341. FTIM1_NOR_TRAD_NOR(0x0f)
  342. #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
  343. FTIM2_NOR_TCH(0x4) | \
  344. FTIM2_NOR_TWP(0x1c)
  345. #define CONFIG_SYS_NOR_FTIM3 0x0
  346. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  347. #define CONFIG_SYS_FLASH_QUIET_TEST
  348. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  349. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  350. #undef CONFIG_SYS_FLASH_CHECKSUM
  351. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  352. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  353. /* CFI for NOR Flash */
  354. #define CONFIG_FLASH_CFI_DRIVER
  355. #define CONFIG_SYS_FLASH_CFI
  356. #define CONFIG_SYS_FLASH_EMPTY_INFO
  357. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  358. /* NAND Flash on IFC */
  359. #define CONFIG_SYS_NAND_BASE 0xff800000
  360. #ifdef CONFIG_PHYS_64BIT
  361. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  362. #else
  363. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  364. #endif
  365. #define CONFIG_MTD_DEVICE
  366. #define CONFIG_MTD_PARTITION
  367. #define CONFIG_CMD_MTDPARTS
  368. #define MTDIDS_DEFAULT "nand0=ff800000.flash"
  369. #define MTDPARTS_DEFAULT \
  370. "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
  371. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  372. | CSPR_PORT_SIZE_8 \
  373. | CSPR_MSEL_NAND \
  374. | CSPR_V)
  375. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  376. #if defined(CONFIG_P1010RDB_PA)
  377. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  378. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  379. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  380. | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
  381. | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
  382. | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
  383. | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
  384. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
  385. #elif defined(CONFIG_P1010RDB_PB)
  386. #define CONFIG_SYS_NAND_ONFI_DETECTION
  387. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  388. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  389. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  390. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  391. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  392. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  393. | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
  394. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  395. #endif
  396. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  397. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  398. #define CONFIG_MTD_NAND_VERIFY_WRITE
  399. #define CONFIG_CMD_NAND
  400. #if defined(CONFIG_P1010RDB_PA)
  401. /* NAND Flash Timing Params */
  402. #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
  403. FTIM0_NAND_TWP(0x0C) | \
  404. FTIM0_NAND_TWCHT(0x04) | \
  405. FTIM0_NAND_TWH(0x05)
  406. #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
  407. FTIM1_NAND_TWBE(0x1d) | \
  408. FTIM1_NAND_TRR(0x07) | \
  409. FTIM1_NAND_TRP(0x0c)
  410. #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
  411. FTIM2_NAND_TREH(0x05) | \
  412. FTIM2_NAND_TWHRE(0x0f)
  413. #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
  414. #elif defined(CONFIG_P1010RDB_PB)
  415. /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
  416. /* ONFI NAND Flash mode0 Timing Params */
  417. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
  418. FTIM0_NAND_TWP(0x18) | \
  419. FTIM0_NAND_TWCHT(0x07) | \
  420. FTIM0_NAND_TWH(0x0a))
  421. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
  422. FTIM1_NAND_TWBE(0x39) | \
  423. FTIM1_NAND_TRR(0x0e) | \
  424. FTIM1_NAND_TRP(0x18))
  425. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  426. FTIM2_NAND_TREH(0x0a) | \
  427. FTIM2_NAND_TWHRE(0x1e))
  428. #define CONFIG_SYS_NAND_FTIM3 0x0
  429. #endif
  430. #define CONFIG_SYS_NAND_DDR_LAW 11
  431. /* Set up IFC registers for boot location NOR/NAND */
  432. #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
  433. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  434. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  435. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  436. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  437. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  438. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  439. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  440. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  441. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  442. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  443. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  444. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  445. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  446. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  447. #else
  448. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  449. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  450. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  451. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  452. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  453. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  454. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  455. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  456. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  457. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  458. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  459. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  460. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  461. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  462. #endif
  463. /* CPLD on IFC */
  464. #define CONFIG_SYS_CPLD_BASE 0xffb00000
  465. #ifdef CONFIG_PHYS_64BIT
  466. #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
  467. #else
  468. #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  469. #endif
  470. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  471. | CSPR_PORT_SIZE_8 \
  472. | CSPR_MSEL_GPCM \
  473. | CSPR_V)
  474. #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
  475. #define CONFIG_SYS_CSOR3 0x0
  476. /* CPLD Timing parameters for IFC CS3 */
  477. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  478. FTIM0_GPCM_TEADC(0x0e) | \
  479. FTIM0_GPCM_TEAHC(0x0e))
  480. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  481. FTIM1_GPCM_TRAD(0x1f))
  482. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  483. FTIM2_GPCM_TCH(0x8) | \
  484. FTIM2_GPCM_TWP(0x1f))
  485. #define CONFIG_SYS_CS3_FTIM3 0x0
  486. #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
  487. defined(CONFIG_RAMBOOT_NAND)
  488. #define CONFIG_SYS_RAMBOOT
  489. #define CONFIG_SYS_EXTRA_ENV_RELOC
  490. #else
  491. #undef CONFIG_SYS_RAMBOOT
  492. #endif
  493. #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
  494. #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
  495. #define CONFIG_A003399_NOR_WORKAROUND
  496. #endif
  497. #endif
  498. #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
  499. #define CONFIG_BOARD_EARLY_INIT_R
  500. #define CONFIG_SYS_INIT_RAM_LOCK
  501. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  502. #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
  503. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
  504. - GENERATED_GBL_DATA_SIZE)
  505. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  506. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  507. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
  508. /*
  509. * Config the L2 Cache as L2 SRAM
  510. */
  511. #if defined(CONFIG_SPL_BUILD)
  512. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  513. #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
  514. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  515. #define CONFIG_SYS_L2_SIZE (256 << 10)
  516. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  517. #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
  518. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  519. #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10)
  520. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
  521. #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
  522. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
  523. #elif defined(CONFIG_NAND)
  524. #ifdef CONFIG_TPL_BUILD
  525. #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
  526. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  527. #define CONFIG_SYS_L2_SIZE (256 << 10)
  528. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  529. #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
  530. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  531. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  532. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  533. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  534. #else
  535. #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
  536. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  537. #define CONFIG_SYS_L2_SIZE (256 << 10)
  538. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  539. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
  540. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  541. #endif
  542. #endif
  543. #endif
  544. /* Serial Port */
  545. #define CONFIG_CONS_INDEX 1
  546. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  547. #define CONFIG_SYS_NS16550
  548. #define CONFIG_SYS_NS16550_SERIAL
  549. #define CONFIG_SYS_NS16550_REG_SIZE 1
  550. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  551. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  552. #define CONFIG_NS16550_MIN_FUNCTIONS
  553. #endif
  554. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
  555. #define CONFIG_SYS_BAUDRATE_TABLE \
  556. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  557. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  558. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  559. /* Use the HUSH parser */
  560. #define CONFIG_SYS_HUSH_PARSER
  561. /*
  562. * Pass open firmware flat tree
  563. */
  564. #define CONFIG_OF_LIBFDT
  565. #define CONFIG_OF_BOARD_SETUP
  566. #define CONFIG_OF_STDOUT_VIA_ALIAS
  567. /* new uImage format support */
  568. #define CONFIG_FIT
  569. #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  570. /* I2C */
  571. #define CONFIG_SYS_I2C
  572. #define CONFIG_SYS_I2C_FSL
  573. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  574. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  575. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  576. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  577. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  578. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  579. #define I2C_PCA9557_ADDR1 0x18
  580. #define I2C_PCA9557_ADDR2 0x19
  581. #define I2C_PCA9557_BUS_NUM 0
  582. /* I2C EEPROM */
  583. #if defined(CONFIG_P1010RDB_PB)
  584. #define CONFIG_ID_EEPROM
  585. #ifdef CONFIG_ID_EEPROM
  586. #define CONFIG_SYS_I2C_EEPROM_NXID
  587. #endif
  588. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  589. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  590. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  591. #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
  592. #endif
  593. /* enable read and write access to EEPROM */
  594. #define CONFIG_CMD_EEPROM
  595. #define CONFIG_SYS_I2C_MULTI_EEPROMS
  596. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  597. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  598. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  599. /* RTC */
  600. #define CONFIG_RTC_PT7C4338
  601. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  602. #define CONFIG_CMD_I2C
  603. /*
  604. * SPI interface will not be available in case of NAND boot SPI CS0 will be
  605. * used for SLIC
  606. */
  607. #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
  608. /* eSPI - Enhanced SPI */
  609. #define CONFIG_FSL_ESPI
  610. #define CONFIG_SPI_FLASH
  611. #define CONFIG_SPI_FLASH_SPANSION
  612. #define CONFIG_CMD_SF
  613. #define CONFIG_SF_DEFAULT_SPEED 10000000
  614. #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  615. #endif
  616. #if defined(CONFIG_TSEC_ENET)
  617. #define CONFIG_MII /* MII PHY management */
  618. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  619. #define CONFIG_TSEC1 1
  620. #define CONFIG_TSEC1_NAME "eTSEC1"
  621. #define CONFIG_TSEC2 1
  622. #define CONFIG_TSEC2_NAME "eTSEC2"
  623. #define CONFIG_TSEC3 1
  624. #define CONFIG_TSEC3_NAME "eTSEC3"
  625. #define TSEC1_PHY_ADDR 1
  626. #define TSEC2_PHY_ADDR 0
  627. #define TSEC3_PHY_ADDR 2
  628. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  629. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  630. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  631. #define TSEC1_PHYIDX 0
  632. #define TSEC2_PHYIDX 0
  633. #define TSEC3_PHYIDX 0
  634. #define CONFIG_ETHPRIME "eTSEC1"
  635. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  636. /* TBI PHY configuration for SGMII mode */
  637. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  638. TBICR_PHY_RESET \
  639. | TBICR_ANEG_ENABLE \
  640. | TBICR_FULL_DUPLEX \
  641. | TBICR_SPEED1_SET \
  642. )
  643. #endif /* CONFIG_TSEC_ENET */
  644. /* SATA */
  645. #define CONFIG_FSL_SATA
  646. #define CONFIG_FSL_SATA_V2
  647. #define CONFIG_LIBATA
  648. #ifdef CONFIG_FSL_SATA
  649. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  650. #define CONFIG_SATA1
  651. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  652. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  653. #define CONFIG_SATA2
  654. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  655. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  656. #define CONFIG_CMD_SATA
  657. #define CONFIG_LBA48
  658. #endif /* #ifdef CONFIG_FSL_SATA */
  659. #define CONFIG_MMC
  660. #ifdef CONFIG_MMC
  661. #define CONFIG_CMD_MMC
  662. #define CONFIG_DOS_PARTITION
  663. #define CONFIG_FSL_ESDHC
  664. #define CONFIG_GENERIC_MMC
  665. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  666. #endif
  667. #define CONFIG_HAS_FSL_DR_USB
  668. #if defined(CONFIG_HAS_FSL_DR_USB)
  669. #define CONFIG_USB_EHCI
  670. #ifdef CONFIG_USB_EHCI
  671. #define CONFIG_CMD_USB
  672. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  673. #define CONFIG_USB_EHCI_FSL
  674. #define CONFIG_USB_STORAGE
  675. #endif
  676. #endif
  677. /*
  678. * Environment
  679. */
  680. #if defined(CONFIG_SDCARD)
  681. #define CONFIG_ENV_IS_IN_MMC
  682. #define CONFIG_FSL_FIXED_MMC_LOCATION
  683. #define CONFIG_SYS_MMC_ENV_DEV 0
  684. #define CONFIG_ENV_SIZE 0x2000
  685. #elif defined(CONFIG_SPIFLASH)
  686. #define CONFIG_ENV_IS_IN_SPI_FLASH
  687. #define CONFIG_ENV_SPI_BUS 0
  688. #define CONFIG_ENV_SPI_CS 0
  689. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  690. #define CONFIG_ENV_SPI_MODE 0
  691. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  692. #define CONFIG_ENV_SECT_SIZE 0x10000
  693. #define CONFIG_ENV_SIZE 0x2000
  694. #elif defined(CONFIG_NAND)
  695. #define CONFIG_ENV_IS_IN_NAND
  696. #ifdef CONFIG_TPL_BUILD
  697. #define CONFIG_ENV_SIZE 0x2000
  698. #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  699. #else
  700. #if defined(CONFIG_P1010RDB_PA)
  701. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  702. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
  703. #elif defined(CONFIG_P1010RDB_PB)
  704. #define CONFIG_ENV_SIZE (16 * 1024)
  705. #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
  706. #endif
  707. #endif
  708. #define CONFIG_ENV_OFFSET (1024 * 1024)
  709. #elif defined(CONFIG_SYS_RAMBOOT)
  710. #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
  711. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  712. #define CONFIG_ENV_SIZE 0x2000
  713. #else
  714. #define CONFIG_ENV_IS_IN_FLASH
  715. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  716. #define CONFIG_ENV_SIZE 0x2000
  717. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  718. #endif
  719. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  720. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  721. /*
  722. * Command line configuration.
  723. */
  724. #include <config_cmd_default.h>
  725. #define CONFIG_CMD_DATE
  726. #define CONFIG_CMD_ERRATA
  727. #define CONFIG_CMD_ELF
  728. #define CONFIG_CMD_IRQ
  729. #define CONFIG_CMD_MII
  730. #define CONFIG_CMD_PING
  731. #define CONFIG_CMD_SETEXPR
  732. #define CONFIG_CMD_REGINFO
  733. #undef CONFIG_WATCHDOG /* watchdog disabled */
  734. #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
  735. || defined(CONFIG_FSL_SATA)
  736. #define CONFIG_CMD_EXT2
  737. #define CONFIG_CMD_FAT
  738. #define CONFIG_DOS_PARTITION
  739. #endif
  740. /*
  741. * Miscellaneous configurable options
  742. */
  743. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  744. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  745. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  746. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  747. #if defined(CONFIG_CMD_KGDB)
  748. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  749. #else
  750. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  751. #endif
  752. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  753. /* Print Buffer Size */
  754. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  755. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  756. /*
  757. * Internal Definitions
  758. *
  759. * Boot Flags
  760. */
  761. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  762. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  763. /*
  764. * For booting Linux, the board info and command line data
  765. * have to be in the first 64 MB of memory, since this is
  766. * the maximum mapped by the Linux kernel during initialization.
  767. */
  768. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
  769. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  770. #if defined(CONFIG_CMD_KGDB)
  771. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  772. #endif
  773. /*
  774. * Environment Configuration
  775. */
  776. #if defined(CONFIG_TSEC_ENET)
  777. #define CONFIG_HAS_ETH0
  778. #define CONFIG_HAS_ETH1
  779. #define CONFIG_HAS_ETH2
  780. #endif
  781. #define CONFIG_ROOTPATH "/opt/nfsroot"
  782. #define CONFIG_BOOTFILE "uImage"
  783. #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
  784. /* default location for tftp and bootm */
  785. #define CONFIG_LOADADDR 1000000
  786. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  787. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  788. #define CONFIG_BAUDRATE 115200
  789. #define CONFIG_EXTRA_ENV_SETTINGS \
  790. "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
  791. "netdev=eth0\0" \
  792. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  793. "loadaddr=1000000\0" \
  794. "consoledev=ttyS0\0" \
  795. "ramdiskaddr=2000000\0" \
  796. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  797. "fdtaddr=c00000\0" \
  798. "fdtfile=p1010rdb.dtb\0" \
  799. "bdev=sda1\0" \
  800. "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
  801. "othbootargs=ramdisk_size=600000\0" \
  802. "usbfatboot=setenv bootargs root=/dev/ram rw " \
  803. "console=$consoledev,$baudrate $othbootargs; " \
  804. "usb start;" \
  805. "fatload usb 0:2 $loadaddr $bootfile;" \
  806. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  807. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  808. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  809. "usbext2boot=setenv bootargs root=/dev/ram rw " \
  810. "console=$consoledev,$baudrate $othbootargs; " \
  811. "usb start;" \
  812. "ext2load usb 0:4 $loadaddr $bootfile;" \
  813. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  814. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  815. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  816. CONFIG_BOOTMODE
  817. #if defined(CONFIG_P1010RDB_PA)
  818. #define CONFIG_BOOTMODE \
  819. "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
  820. "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
  821. "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
  822. "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
  823. "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
  824. "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
  825. #elif defined(CONFIG_P1010RDB_PB)
  826. #define CONFIG_BOOTMODE \
  827. "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
  828. "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
  829. "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
  830. "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
  831. "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
  832. "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
  833. "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
  834. "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
  835. "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
  836. "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
  837. #endif
  838. #define CONFIG_RAMBOOTCOMMAND \
  839. "setenv bootargs root=/dev/ram rw " \
  840. "console=$consoledev,$baudrate $othbootargs; " \
  841. "tftp $ramdiskaddr $ramdiskfile;" \
  842. "tftp $loadaddr $bootfile;" \
  843. "tftp $fdtaddr $fdtfile;" \
  844. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  845. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  846. #include <asm/fsl_secure_boot.h>
  847. #endif /* __CONFIG_H */