MPC8313ERDB.h 21 KB

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  1. /*
  2. * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /*
  7. * mpc8313epb board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * High Level Configuration Options
  13. */
  14. #define CONFIG_E300 1
  15. #define CONFIG_MPC831x 1
  16. #define CONFIG_MPC8313 1
  17. #define CONFIG_MPC8313ERDB 1
  18. #ifdef CONFIG_NAND
  19. #define CONFIG_SPL 1
  20. #define CONFIG_SPL_INIT_MINIMAL
  21. #define CONFIG_SPL_SERIAL_SUPPORT
  22. #define CONFIG_SPL_NAND_SUPPORT
  23. #define CONFIG_SPL_FLUSH_IMAGE
  24. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  25. #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  26. #ifdef CONFIG_SPL_BUILD
  27. #define CONFIG_NS16550_MIN_FUNCTIONS
  28. #endif
  29. #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
  30. #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  31. #define CONFIG_SPL_MAX_SIZE (4 * 1024)
  32. #define CONFIG_SPL_PAD_TO 0x4000
  33. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
  34. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
  35. #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  36. #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
  37. #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  38. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  39. #ifdef CONFIG_SPL_BUILD
  40. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  41. #endif
  42. #endif /* CONFIG_NAND */
  43. #ifndef CONFIG_SYS_TEXT_BASE
  44. #define CONFIG_SYS_TEXT_BASE 0xFE000000
  45. #endif
  46. #ifndef CONFIG_SYS_MONITOR_BASE
  47. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  48. #endif
  49. #define CONFIG_PCI
  50. #define CONFIG_PCI_INDIRECT_BRIDGE
  51. #define CONFIG_FSL_ELBC 1
  52. #define CONFIG_MISC_INIT_R
  53. /*
  54. * On-board devices
  55. *
  56. * TSEC1 is VSC switch
  57. * TSEC2 is SoC TSEC
  58. */
  59. #define CONFIG_VSC7385_ENET
  60. #define CONFIG_TSEC2
  61. #ifdef CONFIG_SYS_66MHZ
  62. #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
  63. #elif defined(CONFIG_SYS_33MHZ)
  64. #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
  65. #else
  66. #error Unknown oscillator frequency.
  67. #endif
  68. #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  69. #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
  70. #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */
  71. #define CONFIG_SYS_IMMR 0xE0000000
  72. #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
  73. #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
  74. #endif
  75. #define CONFIG_SYS_MEMTEST_START 0x00001000
  76. #define CONFIG_SYS_MEMTEST_END 0x07f00000
  77. /* Early revs of this board will lock up hard when attempting
  78. * to access the PMC registers, unless a JTAG debugger is
  79. * connected, or some resistor modifications are made.
  80. */
  81. #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  82. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  83. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  84. /*
  85. * Device configurations
  86. */
  87. /* Vitesse 7385 */
  88. #ifdef CONFIG_VSC7385_ENET
  89. #define CONFIG_TSEC1
  90. /* The flash address and size of the VSC7385 firmware image */
  91. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  92. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  93. #endif
  94. /*
  95. * DDR Setup
  96. */
  97. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  98. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  99. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  100. /*
  101. * Manually set up DDR parameters, as this board does not
  102. * seem to have the SPD connected to I2C.
  103. */
  104. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  105. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  106. | CSCONFIG_ODT_RD_NEVER \
  107. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  108. | CSCONFIG_ROW_BIT_13 \
  109. | CSCONFIG_COL_BIT_10)
  110. /* 0x80010102 */
  111. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  112. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  113. | (0 << TIMING_CFG0_WRT_SHIFT) \
  114. | (0 << TIMING_CFG0_RRT_SHIFT) \
  115. | (0 << TIMING_CFG0_WWT_SHIFT) \
  116. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  117. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  118. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  119. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  120. /* 0x00220802 */
  121. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  122. | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  123. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  124. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  125. | (10 << TIMING_CFG1_REFREC_SHIFT) \
  126. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  127. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  128. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  129. /* 0x3835a322 */
  130. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  131. | (5 << TIMING_CFG2_CPO_SHIFT) \
  132. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  133. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  134. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  135. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  136. | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  137. /* 0x129048c6 */ /* P9-45,may need tuning */
  138. #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
  139. | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  140. /* 0x05100500 */
  141. #if defined(CONFIG_DDR_2T_TIMING)
  142. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  143. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  144. | SDRAM_CFG_DBW_32 \
  145. | SDRAM_CFG_2T_EN)
  146. /* 0x43088000 */
  147. #else
  148. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  149. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  150. | SDRAM_CFG_DBW_32)
  151. /* 0x43080000 */
  152. #endif
  153. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  154. /* set burst length to 8 for 32-bit data path */
  155. #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  156. | (0x0632 << SDRAM_MODE_SD_SHIFT))
  157. /* 0x44480632 */
  158. #define CONFIG_SYS_DDR_MODE_2 0x8000C000
  159. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  160. /*0x02000000*/
  161. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  162. | DDRCDR_PZ_NOMZ \
  163. | DDRCDR_NZ_NOMZ \
  164. | DDRCDR_M_ODR)
  165. /*
  166. * FLASH on the Local Bus
  167. */
  168. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  169. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  170. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  171. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  172. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  173. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  174. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
  175. #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
  176. | BR_PS_16 /* 16 bit port */ \
  177. | BR_MS_GPCM /* MSEL = GPCM */ \
  178. | BR_V) /* valid */
  179. #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  180. | OR_GPCM_XACS \
  181. | OR_GPCM_SCY_9 \
  182. | OR_GPCM_EHTR \
  183. | OR_GPCM_EAD)
  184. /* 0xFF006FF7 TODO SLOW 16 MB flash size */
  185. /* window base at flash base */
  186. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  187. /* 16 MB window size */
  188. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
  189. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  190. #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
  191. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  192. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  193. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
  194. !defined(CONFIG_SPL_BUILD)
  195. #define CONFIG_SYS_RAMBOOT
  196. #endif
  197. #define CONFIG_SYS_INIT_RAM_LOCK 1
  198. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  199. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  200. #define CONFIG_SYS_GBL_DATA_OFFSET \
  201. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  202. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  203. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  204. #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
  205. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  206. /*
  207. * Local Bus LCRR and LBCR regs
  208. */
  209. #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
  210. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  211. #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
  212. | (0xFF << LBCR_BMT_SHIFT) \
  213. | 0xF) /* 0x0004ff0f */
  214. /* LB refresh timer prescal, 266MHz/32 */
  215. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
  216. /* drivers/mtd/nand/nand.c */
  217. #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
  218. #define CONFIG_SYS_NAND_BASE 0xFFF00000
  219. #else
  220. #define CONFIG_SYS_NAND_BASE 0xE2800000
  221. #endif
  222. #define CONFIG_MTD_DEVICE
  223. #define CONFIG_MTD_PARTITION
  224. #define CONFIG_CMD_MTDPARTS
  225. #define MTDIDS_DEFAULT "nand0=e2800000.flash"
  226. #define MTDPARTS_DEFAULT \
  227. "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
  228. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  229. #define CONFIG_MTD_NAND_VERIFY_WRITE
  230. #define CONFIG_CMD_NAND 1
  231. #define CONFIG_NAND_FSL_ELBC 1
  232. #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
  233. #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
  234. #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
  235. | BR_DECC_CHK_GEN /* Use HW ECC */ \
  236. | BR_PS_8 /* 8 bit port */ \
  237. | BR_MS_FCM /* MSEL = FCM */ \
  238. | BR_V) /* valid */
  239. #define CONFIG_SYS_NAND_OR_PRELIM \
  240. (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
  241. | OR_FCM_CSCT \
  242. | OR_FCM_CST \
  243. | OR_FCM_CHT \
  244. | OR_FCM_SCY_1 \
  245. | OR_FCM_TRLX \
  246. | OR_FCM_EHTR)
  247. /* 0xFFFF8396 */
  248. #ifdef CONFIG_NAND
  249. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  250. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
  251. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
  252. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
  253. #else
  254. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
  255. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
  256. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  257. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
  258. #endif
  259. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
  260. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  261. #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
  262. #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
  263. /* local bus write LED / read status buffer (BCSR) mapping */
  264. #define CONFIG_SYS_BCSR_ADDR 0xFA000000
  265. #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
  266. /* map at 0xFA000000 on LCS3 */
  267. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
  268. | BR_PS_8 /* 8 bit port */ \
  269. | BR_MS_GPCM /* MSEL = GPCM */ \
  270. | BR_V) /* valid */
  271. /* 0xFA000801 */
  272. #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
  273. | OR_GPCM_CSNT \
  274. | OR_GPCM_ACS_DIV2 \
  275. | OR_GPCM_XACS \
  276. | OR_GPCM_SCY_15 \
  277. | OR_GPCM_TRLX_SET \
  278. | OR_GPCM_EHTR_SET \
  279. | OR_GPCM_EAD)
  280. /* 0xFFFF8FF7 */
  281. #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
  282. #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  283. /* Vitesse 7385 */
  284. #ifdef CONFIG_VSC7385_ENET
  285. /* VSC7385 Base address on LCS2 */
  286. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  287. #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
  288. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
  289. | BR_PS_8 /* 8 bit port */ \
  290. | BR_MS_GPCM /* MSEL = GPCM */ \
  291. | BR_V) /* valid */
  292. #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
  293. | OR_GPCM_CSNT \
  294. | OR_GPCM_XACS \
  295. | OR_GPCM_SCY_15 \
  296. | OR_GPCM_SETA \
  297. | OR_GPCM_TRLX_SET \
  298. | OR_GPCM_EHTR_SET \
  299. | OR_GPCM_EAD)
  300. /* 0xFFFE09FF */
  301. /* Access window base at VSC7385 base */
  302. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
  303. #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
  304. #endif
  305. /* pass open firmware flat tree */
  306. #define CONFIG_OF_LIBFDT 1
  307. #define CONFIG_OF_BOARD_SETUP 1
  308. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  309. #define CONFIG_MPC83XX_GPIO 1
  310. #define CONFIG_CMD_GPIO 1
  311. /*
  312. * Serial Port
  313. */
  314. #define CONFIG_CONS_INDEX 1
  315. #define CONFIG_SYS_NS16550
  316. #define CONFIG_SYS_NS16550_SERIAL
  317. #define CONFIG_SYS_NS16550_REG_SIZE 1
  318. #define CONFIG_SYS_BAUDRATE_TABLE \
  319. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  320. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  321. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  322. /* Use the HUSH parser */
  323. #define CONFIG_SYS_HUSH_PARSER
  324. /* I2C */
  325. #define CONFIG_SYS_I2C
  326. #define CONFIG_SYS_I2C_FSL
  327. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  328. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  329. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  330. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  331. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  332. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  333. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  334. /*
  335. * General PCI
  336. * Addresses are mapped 1-1.
  337. */
  338. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  339. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  340. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  341. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  342. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  343. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  344. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  345. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  346. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  347. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  348. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  349. /*
  350. * TSEC
  351. */
  352. #define CONFIG_TSEC_ENET /* TSEC ethernet support */
  353. #define CONFIG_GMII /* MII PHY management */
  354. #ifdef CONFIG_TSEC1
  355. #define CONFIG_HAS_ETH0
  356. #define CONFIG_TSEC1_NAME "TSEC0"
  357. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  358. #define TSEC1_PHY_ADDR 0x1c
  359. #define TSEC1_FLAGS TSEC_GIGABIT
  360. #define TSEC1_PHYIDX 0
  361. #endif
  362. #ifdef CONFIG_TSEC2
  363. #define CONFIG_HAS_ETH1
  364. #define CONFIG_TSEC2_NAME "TSEC1"
  365. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  366. #define TSEC2_PHY_ADDR 4
  367. #define TSEC2_FLAGS TSEC_GIGABIT
  368. #define TSEC2_PHYIDX 0
  369. #endif
  370. /* Options are: TSEC[0-1] */
  371. #define CONFIG_ETHPRIME "TSEC1"
  372. /*
  373. * Configure on-board RTC
  374. */
  375. #define CONFIG_RTC_DS1337
  376. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  377. /*
  378. * Environment
  379. */
  380. #if defined(CONFIG_NAND)
  381. #define CONFIG_ENV_IS_IN_NAND 1
  382. #define CONFIG_ENV_OFFSET (512 * 1024)
  383. #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  384. #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  385. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  386. #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
  387. #define CONFIG_ENV_OFFSET_REDUND \
  388. (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
  389. #elif !defined(CONFIG_SYS_RAMBOOT)
  390. #define CONFIG_ENV_IS_IN_FLASH 1
  391. #define CONFIG_ENV_ADDR \
  392. (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  393. #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
  394. #define CONFIG_ENV_SIZE 0x2000
  395. /* Address and size of Redundant Environment Sector */
  396. #else
  397. #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  398. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  399. #define CONFIG_ENV_SIZE 0x2000
  400. #endif
  401. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  402. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  403. /*
  404. * BOOTP options
  405. */
  406. #define CONFIG_BOOTP_BOOTFILESIZE
  407. #define CONFIG_BOOTP_BOOTPATH
  408. #define CONFIG_BOOTP_GATEWAY
  409. #define CONFIG_BOOTP_HOSTNAME
  410. /*
  411. * Command line configuration.
  412. */
  413. #include <config_cmd_default.h>
  414. #define CONFIG_CMD_PING
  415. #define CONFIG_CMD_DHCP
  416. #define CONFIG_CMD_I2C
  417. #define CONFIG_CMD_MII
  418. #define CONFIG_CMD_DATE
  419. #define CONFIG_CMD_PCI
  420. #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
  421. #undef CONFIG_CMD_SAVEENV
  422. #undef CONFIG_CMD_LOADS
  423. #endif
  424. #define CONFIG_CMDLINE_EDITING 1
  425. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  426. /*
  427. * Miscellaneous configurable options
  428. */
  429. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  430. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  431. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  432. /* Print Buffer Size */
  433. #define CONFIG_SYS_PBSIZE \
  434. (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  435. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  436. /* Boot Argument Buffer Size */
  437. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  438. /*
  439. * For booting Linux, the board info and command line data
  440. * have to be in the first 256 MB of memory, since this is
  441. * the maximum mapped by the Linux kernel during initialization.
  442. */
  443. /* Initial Memory map for Linux*/
  444. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  445. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  446. #ifdef CONFIG_SYS_66MHZ
  447. /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
  448. /* 0x62040000 */
  449. #define CONFIG_SYS_HRCW_LOW (\
  450. 0x20000000 /* reserved, must be set */ |\
  451. HRCWL_DDRCM |\
  452. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  453. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  454. HRCWL_CSB_TO_CLKIN_2X1 |\
  455. HRCWL_CORE_TO_CSB_2X1)
  456. #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
  457. #elif defined(CONFIG_SYS_33MHZ)
  458. /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
  459. /* 0x65040000 */
  460. #define CONFIG_SYS_HRCW_LOW (\
  461. 0x20000000 /* reserved, must be set */ |\
  462. HRCWL_DDRCM |\
  463. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  464. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  465. HRCWL_CSB_TO_CLKIN_5X1 |\
  466. HRCWL_CORE_TO_CSB_2X1)
  467. #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
  468. #endif
  469. #define CONFIG_SYS_HRCW_HIGH_BASE (\
  470. HRCWH_PCI_HOST |\
  471. HRCWH_PCI1_ARBITER_ENABLE |\
  472. HRCWH_CORE_ENABLE |\
  473. HRCWH_BOOTSEQ_DISABLE |\
  474. HRCWH_SW_WATCHDOG_DISABLE |\
  475. HRCWH_TSEC1M_IN_RGMII |\
  476. HRCWH_TSEC2M_IN_RGMII |\
  477. HRCWH_BIG_ENDIAN)
  478. #ifdef CONFIG_NAND
  479. #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  480. HRCWH_FROM_0XFFF00100 |\
  481. HRCWH_ROM_LOC_NAND_SP_8BIT |\
  482. HRCWH_RL_EXT_NAND)
  483. #else
  484. #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  485. HRCWH_FROM_0X00000100 |\
  486. HRCWH_ROM_LOC_LOCAL_16BIT |\
  487. HRCWH_RL_EXT_LEGACY)
  488. #endif
  489. /* System IO Config */
  490. #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
  491. /* Enable Internal USB Phy and GPIO on LCD Connector */
  492. #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
  493. #define CONFIG_SYS_HID0_INIT 0x000000000
  494. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
  495. HID0_ENABLE_INSTRUCTION_CACHE | \
  496. HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
  497. #define CONFIG_SYS_HID2 HID2_HBE
  498. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  499. /* DDR @ 0x00000000 */
  500. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
  501. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  502. | BATU_BL_256M \
  503. | BATU_VS \
  504. | BATU_VP)
  505. /* PCI @ 0x80000000 */
  506. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
  507. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
  508. | BATU_BL_256M \
  509. | BATU_VS \
  510. | BATU_VP)
  511. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
  512. | BATL_PP_RW \
  513. | BATL_CACHEINHIBIT \
  514. | BATL_GUARDEDSTORAGE)
  515. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
  516. | BATU_BL_256M \
  517. | BATU_VS \
  518. | BATU_VP)
  519. /* PCI2 not supported on 8313 */
  520. #define CONFIG_SYS_IBAT3L (0)
  521. #define CONFIG_SYS_IBAT3U (0)
  522. #define CONFIG_SYS_IBAT4L (0)
  523. #define CONFIG_SYS_IBAT4U (0)
  524. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
  525. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
  526. | BATL_PP_RW \
  527. | BATL_CACHEINHIBIT \
  528. | BATL_GUARDEDSTORAGE)
  529. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
  530. | BATU_BL_256M \
  531. | BATU_VS \
  532. | BATU_VP)
  533. /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  534. #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  535. #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  536. #define CONFIG_SYS_IBAT7L (0)
  537. #define CONFIG_SYS_IBAT7U (0)
  538. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  539. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  540. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  541. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  542. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  543. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  544. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  545. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  546. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  547. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  548. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  549. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  550. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  551. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  552. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  553. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  554. /*
  555. * Environment Configuration
  556. */
  557. #define CONFIG_ENV_OVERWRITE
  558. #define CONFIG_NETDEV "eth1"
  559. #define CONFIG_HOSTNAME mpc8313erdb
  560. #define CONFIG_ROOTPATH "/nfs/root/path"
  561. #define CONFIG_BOOTFILE "uImage"
  562. /* U-Boot image on TFTP server */
  563. #define CONFIG_UBOOTPATH "u-boot.bin"
  564. #define CONFIG_FDTFILE "mpc8313erdb.dtb"
  565. /* default location for tftp and bootm */
  566. #define CONFIG_LOADADDR 800000
  567. #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
  568. #define CONFIG_BAUDRATE 115200
  569. #define CONFIG_EXTRA_ENV_SETTINGS \
  570. "netdev=" CONFIG_NETDEV "\0" \
  571. "ethprime=TSEC1\0" \
  572. "uboot=" CONFIG_UBOOTPATH "\0" \
  573. "tftpflash=tftpboot $loadaddr $uboot; " \
  574. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  575. " +$filesize; " \
  576. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  577. " +$filesize; " \
  578. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  579. " $filesize; " \
  580. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  581. " +$filesize; " \
  582. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  583. " $filesize\0" \
  584. "fdtaddr=780000\0" \
  585. "fdtfile=" CONFIG_FDTFILE "\0" \
  586. "console=ttyS0\0" \
  587. "setbootargs=setenv bootargs " \
  588. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  589. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  590. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
  591. "$netdev:off " \
  592. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  593. #define CONFIG_NFSBOOTCOMMAND \
  594. "setenv rootdev /dev/nfs;" \
  595. "run setbootargs;" \
  596. "run setipargs;" \
  597. "tftp $loadaddr $bootfile;" \
  598. "tftp $fdtaddr $fdtfile;" \
  599. "bootm $loadaddr - $fdtaddr"
  600. #define CONFIG_RAMBOOTCOMMAND \
  601. "setenv rootdev /dev/ram;" \
  602. "run setbootargs;" \
  603. "tftp $ramdiskaddr $ramdiskfile;" \
  604. "tftp $loadaddr $bootfile;" \
  605. "tftp $fdtaddr $fdtfile;" \
  606. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  607. #endif /* __CONFIG_H */