C29XPCIE.h 18 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /*
  7. * C29XPCIE board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #define CONFIG_PHYS_64BIT
  12. #ifdef CONFIG_C29XPCIE
  13. #define CONFIG_PPC_C29X
  14. #endif
  15. #ifdef CONFIG_SPIFLASH
  16. #define CONFIG_RAMBOOT_SPIFLASH
  17. #define CONFIG_SYS_TEXT_BASE 0x11000000
  18. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  19. #endif
  20. #ifdef CONFIG_NAND
  21. #define CONFIG_SPL 1
  22. #define CONFIG_TPL 1
  23. #ifdef CONFIG_TPL_BUILD
  24. #define CONFIG_SPL_NAND_BOOT
  25. #define CONFIG_SPL_FLUSH_IMAGE
  26. #define CONFIG_SPL_ENV_SUPPORT
  27. #define CONFIG_SPL_NAND_INIT
  28. #define CONFIG_SPL_SERIAL_SUPPORT
  29. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  30. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  31. #define CONFIG_SPL_I2C_SUPPORT
  32. #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  33. #define CONFIG_SPL_NAND_SUPPORT
  34. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  35. #define CONFIG_SPL_COMMON_INIT_DDR
  36. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  37. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  38. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  39. #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
  40. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  41. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  42. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  43. #elif defined(CONFIG_SPL_BUILD)
  44. #define CONFIG_SPL_INIT_MINIMAL
  45. #define CONFIG_SPL_SERIAL_SUPPORT
  46. #define CONFIG_SPL_NAND_SUPPORT
  47. #define CONFIG_SPL_NAND_MINIMAL
  48. #define CONFIG_SPL_FLUSH_IMAGE
  49. #define CONFIG_SPL_TEXT_BASE 0xff800000
  50. #define CONFIG_SPL_MAX_SIZE 8192
  51. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  52. #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
  53. #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
  54. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  55. #endif
  56. #define CONFIG_SPL_PAD_TO 0x20000
  57. #define CONFIG_TPL_PAD_TO 0x20000
  58. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  59. #define CONFIG_SYS_TEXT_BASE 0x11001000
  60. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  61. #endif
  62. #ifndef CONFIG_SYS_TEXT_BASE
  63. #define CONFIG_SYS_TEXT_BASE 0xeff40000
  64. #endif
  65. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  66. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  67. #endif
  68. #ifdef CONFIG_SPL_BUILD
  69. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  70. #else
  71. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  72. #endif
  73. #ifdef CONFIG_SPL_BUILD
  74. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  75. #endif
  76. /* High Level Configuration Options */
  77. #define CONFIG_BOOKE /* BOOKE */
  78. #define CONFIG_E500 /* BOOKE e500 family */
  79. #define CONFIG_FSL_IFC /* Enable IFC Support */
  80. #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
  81. #define CONFIG_PCI /* Enable PCI/PCIE */
  82. #ifdef CONFIG_PCI
  83. #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
  84. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  85. #define CONFIG_PCI_INDIRECT_BRIDGE
  86. #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  87. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  88. #define CONFIG_CMD_NET
  89. #define CONFIG_CMD_PCI
  90. #define CONFIG_E1000
  91. /*
  92. * PCI Windows
  93. * Memory space is mapped 1-1, but I/O space must start from 0.
  94. */
  95. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  96. #define CONFIG_SYS_PCIE1_NAME "Slot 1"
  97. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  98. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  99. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  100. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  101. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  102. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  103. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  104. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
  105. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  106. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  107. #define CONFIG_DOS_PARTITION
  108. #endif
  109. #define CONFIG_FSL_LAW /* Use common FSL init code */
  110. #define CONFIG_TSEC_ENET
  111. #define CONFIG_ENV_OVERWRITE
  112. #define CONFIG_DDR_CLK_FREQ 100000000
  113. #define CONFIG_SYS_CLK_FREQ 66666666
  114. #define CONFIG_HWCONFIG
  115. /*
  116. * These can be toggled for performance analysis, otherwise use default.
  117. */
  118. #define CONFIG_L2_CACHE /* toggle L2 cache */
  119. #define CONFIG_BTB /* toggle branch predition */
  120. #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
  121. #define CONFIG_ENABLE_36BIT_PHYS
  122. #define CONFIG_ADDR_MAP 1
  123. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  124. #define CONFIG_SYS_MEMTEST_START 0x00200000
  125. #define CONFIG_SYS_MEMTEST_END 0x00400000
  126. #define CONFIG_PANIC_HANG
  127. /* DDR Setup */
  128. #define CONFIG_SYS_FSL_DDR3
  129. #define CONFIG_DDR_SPD
  130. #define CONFIG_SYS_SPD_BUS_NUM 0
  131. #define SPD_EEPROM_ADDRESS 0x50
  132. #define CONFIG_SYS_DDR_RAW_TIMING
  133. /* DDR ECC Setup*/
  134. #define CONFIG_DDR_ECC
  135. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  136. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  137. #define CONFIG_SYS_SDRAM_SIZE 512
  138. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  139. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  140. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  141. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  142. #define CONFIG_SYS_CCSRBAR 0xffe00000
  143. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  144. /* Platform SRAM setting */
  145. #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
  146. #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
  147. (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
  148. #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
  149. #ifdef CONFIG_SPL_BUILD
  150. #define CONFIG_SYS_NO_FLASH
  151. #endif
  152. /*
  153. * IFC Definitions
  154. */
  155. /* NOR Flash on IFC */
  156. #define CONFIG_SYS_FLASH_BASE 0xec000000
  157. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
  158. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  159. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
  160. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  161. #define CONFIG_SYS_FLASH_QUIET_TEST
  162. #define CONFIG_FLASH_SHOW_PROGRESS 45
  163. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
  164. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
  165. /* 16Bit NOR Flash - S29GL512S10TFI01 */
  166. #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  167. CSPR_PORT_SIZE_16 | \
  168. CSPR_MSEL_NOR | \
  169. CSPR_V)
  170. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
  171. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
  172. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  173. FTIM0_NOR_TEADC(0x5) | \
  174. FTIM0_NOR_TEAHC(0x5))
  175. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  176. FTIM1_NOR_TRAD_NOR(0x1A) |\
  177. FTIM1_NOR_TSEQRAD_NOR(0x13))
  178. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  179. FTIM2_NOR_TCH(0x4) | \
  180. FTIM2_NOR_TWPH(0x0E) | \
  181. FTIM2_NOR_TWP(0x1c))
  182. #define CONFIG_SYS_NOR_FTIM3 0x0
  183. /* CFI for NOR Flash */
  184. #define CONFIG_FLASH_CFI_DRIVER
  185. #define CONFIG_SYS_FLASH_CFI
  186. #define CONFIG_SYS_FLASH_EMPTY_INFO
  187. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  188. /* NAND Flash on IFC */
  189. #define CONFIG_NAND_FSL_IFC
  190. #define CONFIG_SYS_NAND_BASE 0xff800000
  191. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  192. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  193. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  194. #define CONFIG_MTD_NAND_VERIFY_WRITE
  195. #define CONFIG_CMD_NAND
  196. #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
  197. /* 8Bit NAND Flash - K9F1G08U0B */
  198. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  199. | CSPR_PORT_SIZE_8 \
  200. | CSPR_MSEL_NAND \
  201. | CSPR_V)
  202. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  203. #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
  204. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  205. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  206. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  207. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  208. | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
  209. | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
  210. | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
  211. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
  212. FTIM0_NAND_TWP(0x0c) | \
  213. FTIM0_NAND_TWCHT(0x08) | \
  214. FTIM0_NAND_TWH(0x06))
  215. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
  216. FTIM1_NAND_TWBE(0x1d) | \
  217. FTIM1_NAND_TRR(0x08) | \
  218. FTIM1_NAND_TRP(0x0c))
  219. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
  220. FTIM2_NAND_TREH(0x0a) | \
  221. FTIM2_NAND_TWHRE(0x18))
  222. #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
  223. #define CONFIG_SYS_NAND_DDR_LAW 11
  224. /* Set up IFC registers for boot location NOR/NAND */
  225. #ifdef CONFIG_NAND
  226. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  227. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  228. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  229. #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
  230. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  231. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  232. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  233. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  234. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  235. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  236. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  237. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  238. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  239. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  240. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  241. #else
  242. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  243. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  244. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  245. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  246. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  247. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  248. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  249. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  250. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  251. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  252. #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
  253. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  254. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  255. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  256. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  257. #endif
  258. /* CPLD on IFC, selected by CS2 */
  259. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  260. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
  261. | CONFIG_SYS_CPLD_BASE)
  262. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  263. | CSPR_PORT_SIZE_8 \
  264. | CSPR_MSEL_GPCM \
  265. | CSPR_V)
  266. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  267. #define CONFIG_SYS_CSOR2 0x0
  268. /* CPLD Timing parameters for IFC CS2 */
  269. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  270. FTIM0_GPCM_TEADC(0x0e) | \
  271. FTIM0_GPCM_TEAHC(0x0e))
  272. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  273. FTIM1_GPCM_TRAD(0x1f))
  274. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  275. FTIM2_GPCM_TCH(0x8) | \
  276. FTIM2_GPCM_TWP(0x1f))
  277. #define CONFIG_SYS_CS2_FTIM3 0x0
  278. #if defined(CONFIG_RAMBOOT_SPIFLASH)
  279. #define CONFIG_SYS_RAMBOOT
  280. #define CONFIG_SYS_EXTRA_ENV_RELOC
  281. #endif
  282. #define CONFIG_BOARD_EARLY_INIT_R
  283. #define CONFIG_SYS_INIT_RAM_LOCK
  284. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
  285. #define CONFIG_SYS_INIT_RAM_END 0x00004000
  286. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
  287. - GENERATED_GBL_DATA_SIZE)
  288. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  289. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  290. #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
  291. /*
  292. * Config the L2 Cache as L2 SRAM
  293. */
  294. #if defined(CONFIG_SPL_BUILD)
  295. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  296. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  297. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  298. #define CONFIG_SYS_L2_SIZE (256 << 10)
  299. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  300. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  301. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
  302. #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
  303. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
  304. #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
  305. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  306. #elif defined(CONFIG_NAND)
  307. #ifdef CONFIG_TPL_BUILD
  308. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  309. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  310. #define CONFIG_SYS_L2_SIZE (256 << 10)
  311. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  312. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  313. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  314. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  315. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  316. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  317. #else
  318. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  319. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  320. #define CONFIG_SYS_L2_SIZE (256 << 10)
  321. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  322. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
  323. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  324. #endif
  325. #endif
  326. #endif
  327. /* Serial Port */
  328. #define CONFIG_CONS_INDEX 1
  329. #define CONFIG_SYS_NS16550
  330. #define CONFIG_SYS_NS16550_SERIAL
  331. #define CONFIG_SYS_NS16550_REG_SIZE 1
  332. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  333. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  334. #define CONFIG_NS16550_MIN_FUNCTIONS
  335. #endif
  336. #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
  337. #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  338. #define CONFIG_SYS_BAUDRATE_TABLE \
  339. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  340. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  341. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  342. /* Use the HUSH parser */
  343. #define CONFIG_SYS_HUSH_PARSER
  344. /*
  345. * Pass open firmware flat tree
  346. */
  347. #define CONFIG_OF_LIBFDT
  348. #define CONFIG_OF_BOARD_SETUP
  349. #define CONFIG_OF_STDOUT_VIA_ALIAS
  350. /* new uImage format support */
  351. #define CONFIG_FIT
  352. #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  353. #define CONFIG_SYS_I2C
  354. #define CONFIG_SYS_I2C_FSL
  355. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  356. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  357. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  358. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  359. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  360. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  361. /* I2C EEPROM */
  362. /* enable read and write access to EEPROM */
  363. #define CONFIG_CMD_EEPROM
  364. #define CONFIG_SYS_I2C_MULTI_EEPROMS
  365. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  366. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  367. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  368. #define CONFIG_CMD_I2C
  369. /* eSPI - Enhanced SPI */
  370. #define CONFIG_FSL_ESPI
  371. #define CONFIG_SPI_FLASH
  372. #define CONFIG_SPI_FLASH_SPANSION
  373. #define CONFIG_SPI_FLASH_EON
  374. #define CONFIG_CMD_SF
  375. #define CONFIG_SF_DEFAULT_SPEED 10000000
  376. #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  377. #ifdef CONFIG_TSEC_ENET
  378. #define CONFIG_NET_MULTI
  379. #define CONFIG_MII /* MII PHY management */
  380. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  381. #define CONFIG_TSEC1 1
  382. #define CONFIG_TSEC1_NAME "eTSEC1"
  383. #define CONFIG_TSEC2 1
  384. #define CONFIG_TSEC2_NAME "eTSEC2"
  385. /* Default mode is RGMII mode */
  386. #define TSEC1_PHY_ADDR 0
  387. #define TSEC2_PHY_ADDR 2
  388. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  389. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  390. #define CONFIG_ETHPRIME "eTSEC1"
  391. #define CONFIG_PHY_GIGE
  392. #endif /* CONFIG_TSEC_ENET */
  393. /*
  394. * Environment
  395. */
  396. #if defined(CONFIG_SYS_RAMBOOT)
  397. #if defined(CONFIG_RAMBOOT_SPIFLASH)
  398. #define CONFIG_ENV_IS_IN_SPI_FLASH
  399. #define CONFIG_ENV_SPI_BUS 0
  400. #define CONFIG_ENV_SPI_CS 0
  401. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  402. #define CONFIG_ENV_SPI_MODE 0
  403. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  404. #define CONFIG_ENV_SECT_SIZE 0x10000
  405. #define CONFIG_ENV_SIZE 0x2000
  406. #endif
  407. #elif defined(CONFIG_NAND)
  408. #define CONFIG_ENV_IS_IN_NAND
  409. #ifdef CONFIG_TPL_BUILD
  410. #define CONFIG_ENV_SIZE 0x2000
  411. #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  412. #else
  413. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  414. #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
  415. #endif
  416. #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
  417. #else
  418. #define CONFIG_ENV_IS_IN_FLASH
  419. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  420. #define CONFIG_ENV_SIZE 0x2000
  421. #define CONFIG_ENV_SECT_SIZE 0x20000
  422. #endif
  423. #define CONFIG_LOADS_ECHO
  424. #define CONFIG_SYS_LOADS_BAUD_CHANGE
  425. /*
  426. * Command line configuration.
  427. */
  428. #include <config_cmd_default.h>
  429. #define CONFIG_CMD_ERRATA
  430. #define CONFIG_CMD_ELF
  431. #define CONFIG_CMD_IRQ
  432. #define CONFIG_CMD_MII
  433. #define CONFIG_CMD_PING
  434. #define CONFIG_CMD_SETEXPR
  435. #define CONFIG_CMD_REGINFO
  436. /*
  437. * Miscellaneous configurable options
  438. */
  439. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  440. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  441. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  442. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  443. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  444. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  445. /* Print Buffer Size */
  446. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  447. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  448. /*
  449. * For booting Linux, the board info and command line data
  450. * have to be in the first 64 MB of memory, since this is
  451. * the maximum mapped by the Linux kernel during initialization.
  452. */
  453. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
  454. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  455. /*
  456. * Environment Configuration
  457. */
  458. #ifdef CONFIG_TSEC_ENET
  459. #define CONFIG_HAS_ETH0
  460. #define CONFIG_HAS_ETH1
  461. #endif
  462. #define CONFIG_ROOTPATH "/opt/nfsroot"
  463. #define CONFIG_BOOTFILE "uImage"
  464. #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
  465. /* default location for tftp and bootm */
  466. #define CONFIG_LOADADDR 1000000
  467. #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
  468. #define CONFIG_BAUDRATE 115200
  469. #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
  470. #define CONFIG_EXTRA_ENV_SETTINGS \
  471. "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
  472. "netdev=eth0\0" \
  473. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  474. "loadaddr=1000000\0" \
  475. "consoledev=ttyS0\0" \
  476. "ramdiskaddr=2000000\0" \
  477. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  478. "fdtaddr=c00000\0" \
  479. "fdtfile=name/of/device-tree.dtb\0" \
  480. "othbootargs=ramdisk_size=600000\0" \
  481. #define CONFIG_RAMBOOTCOMMAND \
  482. "setenv bootargs root=/dev/ram rw " \
  483. "console=$consoledev,$baudrate $othbootargs; " \
  484. "tftp $ramdiskaddr $ramdiskfile;" \
  485. "tftp $loadaddr $bootfile;" \
  486. "tftp $fdtaddr $fdtfile;" \
  487. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  488. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  489. #endif /* __CONFIG_H */