BSC9132QDS.h 22 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /*
  7. * BSC9132 QDS board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #ifdef CONFIG_BSC9132QDS
  12. #define CONFIG_BSC9132
  13. #endif
  14. #define CONFIG_MISC_INIT_R
  15. #ifdef CONFIG_SDCARD
  16. #define CONFIG_RAMBOOT_SDCARD
  17. #define CONFIG_SYS_RAMBOOT
  18. #define CONFIG_SYS_EXTRA_ENV_RELOC
  19. #define CONFIG_SYS_TEXT_BASE 0x11000000
  20. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  21. #endif
  22. #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
  23. #ifdef CONFIG_SPIFLASH
  24. #define CONFIG_RAMBOOT_SPIFLASH
  25. #define CONFIG_SYS_RAMBOOT
  26. #define CONFIG_SYS_EXTRA_ENV_RELOC
  27. #define CONFIG_SYS_TEXT_BASE 0x11000000
  28. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  29. #endif
  30. #ifdef CONFIG_NAND_SECBOOT
  31. #define CONFIG_RAMBOOT_NAND
  32. #define CONFIG_SYS_RAMBOOT
  33. #define CONFIG_SYS_EXTRA_ENV_RELOC
  34. #define CONFIG_SYS_TEXT_BASE 0x11000000
  35. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  36. #endif
  37. #ifdef CONFIG_NAND
  38. #define CONFIG_SPL 1
  39. #define CONFIG_SPL_INIT_MINIMAL
  40. #define CONFIG_SPL_SERIAL_SUPPORT
  41. #define CONFIG_SPL_NAND_SUPPORT
  42. #define CONFIG_SPL_NAND_BOOT
  43. #define CONFIG_SPL_FLUSH_IMAGE
  44. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  45. #define CONFIG_SYS_TEXT_BASE 0x00201000
  46. #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
  47. #define CONFIG_SPL_MAX_SIZE 8192
  48. #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
  49. #define CONFIG_SPL_RELOC_STACK 0x00100000
  50. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
  51. #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
  52. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  53. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
  54. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  55. #endif
  56. #ifndef CONFIG_SYS_TEXT_BASE
  57. #define CONFIG_SYS_TEXT_BASE 0x8ff40000
  58. #endif
  59. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  60. #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
  61. #endif
  62. #ifdef CONFIG_SPL_BUILD
  63. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  64. #else
  65. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  66. #endif
  67. /* High Level Configuration Options */
  68. #define CONFIG_BOOKE /* BOOKE */
  69. #define CONFIG_E500 /* BOOKE e500 family */
  70. #define CONFIG_FSL_IFC /* Enable IFC Support */
  71. #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
  72. #define CONFIG_PCI /* Enable PCI/PCIE */
  73. #if defined(CONFIG_PCI)
  74. #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
  75. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  76. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  77. #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  78. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  79. #define CONFIG_CMD_NET
  80. #define CONFIG_CMD_PCI
  81. #define CONFIG_E1000 /* E1000 pci Ethernet card*/
  82. /*
  83. * PCI Windows
  84. * Memory space is mapped 1-1, but I/O space must start from 0.
  85. */
  86. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  87. #define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
  88. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
  89. #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
  90. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
  91. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  92. #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
  93. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  94. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  95. #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
  96. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  97. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  98. #define CONFIG_DOS_PARTITION
  99. #endif
  100. #define CONFIG_FSL_LAW /* Use common FSL init code */
  101. #define CONFIG_ENV_OVERWRITE
  102. #define CONFIG_TSEC_ENET /* ethernet */
  103. #if defined(CONFIG_SYS_CLK_100_DDR_100)
  104. #define CONFIG_SYS_CLK_FREQ 100000000
  105. #define CONFIG_DDR_CLK_FREQ 100000000
  106. #elif defined(CONFIG_SYS_CLK_100_DDR_133)
  107. #define CONFIG_SYS_CLK_FREQ 100000000
  108. #define CONFIG_DDR_CLK_FREQ 133000000
  109. #endif
  110. #define CONFIG_MP
  111. #define CONFIG_HWCONFIG
  112. /*
  113. * These can be toggled for performance analysis, otherwise use default.
  114. */
  115. #define CONFIG_L2_CACHE /* toggle L2 cache */
  116. #define CONFIG_BTB /* enable branch predition */
  117. #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
  118. #define CONFIG_SYS_MEMTEST_END 0x01ffffff
  119. /* DDR Setup */
  120. #define CONFIG_SYS_FSL_DDR3
  121. #define CONFIG_SYS_SPD_BUS_NUM 0
  122. #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
  123. #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
  124. #define CONFIG_FSL_DDR_INTERACTIVE
  125. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  126. #define CONFIG_SYS_SDRAM_SIZE (1024)
  127. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  128. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  129. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  130. /* DDR3 Controller Settings */
  131. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  132. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
  133. #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
  134. #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
  135. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  136. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  137. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  138. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  139. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  140. #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
  141. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  142. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  143. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  144. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  145. #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
  146. #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
  147. #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
  148. #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
  149. #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
  150. #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
  151. #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
  152. #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
  153. #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
  154. #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
  155. #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
  156. #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
  157. #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
  158. #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
  159. #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
  160. #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
  161. #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
  162. #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
  163. #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
  164. #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
  165. #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
  166. #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
  167. #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
  168. #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
  169. #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
  170. #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
  171. /*FIXME: the following params are constant w.r.t diff freq
  172. combinations. this should be removed later
  173. */
  174. #if CONFIG_DDR_CLK_FREQ == 100000000
  175. #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
  176. #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
  177. #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
  178. #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
  179. #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
  180. #elif CONFIG_DDR_CLK_FREQ == 133000000
  181. #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
  182. #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
  183. #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
  184. #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
  185. #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
  186. #else
  187. #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
  188. #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
  189. #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
  190. #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
  191. #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
  192. #endif
  193. /* relocated CCSRBAR */
  194. #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
  195. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
  196. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
  197. /* DSP CCSRBAR */
  198. #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
  199. #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
  200. /*
  201. * IFC Definitions
  202. */
  203. /* NOR Flash on IFC */
  204. #ifdef CONFIG_SPL_BUILD
  205. #define CONFIG_SYS_NO_FLASH
  206. #endif
  207. #define CONFIG_SYS_FLASH_BASE 0x88000000
  208. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
  209. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  210. #define CONFIG_SYS_NOR_CSPR 0x88000101
  211. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  212. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
  213. /* NOR Flash Timing Params */
  214. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
  215. | FTIM0_NOR_TEADC(0x03) \
  216. | FTIM0_NOR_TAVDS(0x00) \
  217. | FTIM0_NOR_TEAHC(0x0f))
  218. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
  219. | FTIM1_NOR_TRAD_NOR(0x09) \
  220. | FTIM1_NOR_TSEQRAD_NOR(0x09))
  221. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
  222. | FTIM2_NOR_TCH(0x4) \
  223. | FTIM2_NOR_TWPH(0x7) \
  224. | FTIM2_NOR_TWP(0x1e))
  225. #define CONFIG_SYS_NOR_FTIM3 0x0
  226. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  227. #define CONFIG_SYS_FLASH_QUIET_TEST
  228. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  229. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  230. #undef CONFIG_SYS_FLASH_CHECKSUM
  231. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  232. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  233. /* CFI for NOR Flash */
  234. #define CONFIG_FLASH_CFI_DRIVER
  235. #define CONFIG_SYS_FLASH_CFI
  236. #define CONFIG_SYS_FLASH_EMPTY_INFO
  237. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  238. /* NAND Flash on IFC */
  239. #define CONFIG_SYS_NAND_BASE 0xff800000
  240. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  241. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  242. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  243. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  244. | CSPR_V)
  245. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  246. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  247. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  248. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  249. | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
  250. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  251. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  252. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  253. /* NAND Flash Timing Params */
  254. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
  255. | FTIM0_NAND_TWP(0x05) \
  256. | FTIM0_NAND_TWCHT(0x02) \
  257. | FTIM0_NAND_TWH(0x04))
  258. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
  259. | FTIM1_NAND_TWBE(0x1e) \
  260. | FTIM1_NAND_TRR(0x07) \
  261. | FTIM1_NAND_TRP(0x05))
  262. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
  263. | FTIM2_NAND_TREH(0x04) \
  264. | FTIM2_NAND_TWHRE(0x11))
  265. #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
  266. #define CONFIG_SYS_NAND_DDR_LAW 11
  267. /* NAND */
  268. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  269. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  270. #define CONFIG_MTD_NAND_VERIFY_WRITE
  271. #define CONFIG_CMD_NAND
  272. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  273. #ifndef CONFIG_SPL_BUILD
  274. #define CONFIG_FSL_QIXIS
  275. #endif
  276. #ifdef CONFIG_FSL_QIXIS
  277. #define CONFIG_SYS_FPGA_BASE 0xffb00000
  278. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  279. #define QIXIS_BASE CONFIG_SYS_FPGA_BASE
  280. #define QIXIS_LBMAP_SWITCH 9
  281. #define QIXIS_LBMAP_MASK 0x07
  282. #define QIXIS_LBMAP_SHIFT 0
  283. #define QIXIS_LBMAP_DFLTBANK 0x00
  284. #define QIXIS_LBMAP_ALTBANK 0x04
  285. #define QIXIS_RST_CTL_RESET 0x83
  286. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  287. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  288. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  289. #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
  290. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
  291. | CSPR_PORT_SIZE_8 \
  292. | CSPR_MSEL_GPCM \
  293. | CSPR_V)
  294. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  295. #define CONFIG_SYS_CSOR2 0x0
  296. /* CPLD Timing parameters for IFC CS3 */
  297. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  298. FTIM0_GPCM_TEADC(0x0e) | \
  299. FTIM0_GPCM_TEAHC(0x0e))
  300. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  301. FTIM1_GPCM_TRAD(0x1f))
  302. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  303. FTIM2_GPCM_TCH(0x8) | \
  304. FTIM2_GPCM_TWP(0x1f))
  305. #define CONFIG_SYS_CS2_FTIM3 0x0
  306. #endif
  307. /* Set up IFC registers for boot location NOR/NAND */
  308. #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
  309. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  310. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  311. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  312. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  313. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  314. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  315. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  316. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  317. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  318. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  319. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  320. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  321. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  322. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  323. #else
  324. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  325. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  326. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  327. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  328. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  329. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  330. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  331. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  332. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  333. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  334. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  335. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  336. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  337. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  338. #endif
  339. #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
  340. #define CONFIG_BOARD_EARLY_INIT_R
  341. #define CONFIG_SYS_INIT_RAM_LOCK
  342. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  343. #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
  344. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
  345. - GENERATED_GBL_DATA_SIZE)
  346. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  347. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  348. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
  349. /* Serial Port */
  350. #define CONFIG_CONS_INDEX 1
  351. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  352. #define CONFIG_SYS_NS16550
  353. #define CONFIG_SYS_NS16550_SERIAL
  354. #define CONFIG_SYS_NS16550_REG_SIZE 1
  355. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  356. #ifdef CONFIG_SPL_BUILD
  357. #define CONFIG_NS16550_MIN_FUNCTIONS
  358. #endif
  359. #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
  360. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
  361. #define CONFIG_SYS_BAUDRATE_TABLE \
  362. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  363. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
  364. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
  365. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
  366. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
  367. /* Use the HUSH parser */
  368. #define CONFIG_SYS_HUSH_PARSER /* hush parser */
  369. #ifdef CONFIG_SYS_HUSH_PARSER
  370. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  371. #endif
  372. /*
  373. * Pass open firmware flat tree
  374. */
  375. #define CONFIG_OF_LIBFDT
  376. #define CONFIG_OF_BOARD_SETUP
  377. #define CONFIG_OF_STDOUT_VIA_ALIAS
  378. /* new uImage format support */
  379. #define CONFIG_FIT
  380. #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  381. #define CONFIG_SYS_I2C
  382. #define CONFIG_SYS_I2C_FSL
  383. #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
  384. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  385. #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
  386. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  387. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  388. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  389. /* I2C EEPROM */
  390. #define CONFIG_ID_EEPROM
  391. #ifdef CONFIG_ID_EEPROM
  392. #define CONFIG_SYS_I2C_EEPROM_NXID
  393. #endif
  394. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  395. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  396. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  397. /* enable read and write access to EEPROM */
  398. #define CONFIG_CMD_EEPROM
  399. #define CONFIG_SYS_I2C_MULTI_EEPROMS
  400. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  401. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  402. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  403. /* I2C FPGA */
  404. #define CONFIG_I2C_FPGA
  405. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  406. #define CONFIG_RTC_DS3231
  407. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  408. /*
  409. * SPI interface will not be available in case of NAND boot SPI CS0 will be
  410. * used for SLIC
  411. */
  412. /* eSPI - Enhanced SPI */
  413. #define CONFIG_FSL_ESPI /* SPI */
  414. #ifdef CONFIG_FSL_ESPI
  415. #define CONFIG_SPI_FLASH
  416. #define CONFIG_SPI_FLASH_SPANSION
  417. #define CONFIG_CMD_SF
  418. #define CONFIG_SF_DEFAULT_SPEED 10000000
  419. #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  420. #endif
  421. #if defined(CONFIG_TSEC_ENET)
  422. #define CONFIG_MII /* MII PHY management */
  423. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  424. #define CONFIG_TSEC1 1
  425. #define CONFIG_TSEC1_NAME "eTSEC1"
  426. #define CONFIG_TSEC2 1
  427. #define CONFIG_TSEC2_NAME "eTSEC2"
  428. #define TSEC1_PHY_ADDR 0
  429. #define TSEC2_PHY_ADDR 1
  430. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  431. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  432. #define TSEC1_PHYIDX 0
  433. #define TSEC2_PHYIDX 0
  434. #define CONFIG_ETHPRIME "eTSEC1"
  435. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  436. /* TBI PHY configuration for SGMII mode */
  437. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  438. TBICR_PHY_RESET \
  439. | TBICR_ANEG_ENABLE \
  440. | TBICR_FULL_DUPLEX \
  441. | TBICR_SPEED1_SET \
  442. )
  443. #endif /* CONFIG_TSEC_ENET */
  444. #define CONFIG_MMC
  445. #ifdef CONFIG_MMC
  446. #define CONFIG_CMD_MMC
  447. #define CONFIG_DOS_PARTITION
  448. #define CONFIG_FSL_ESDHC
  449. #define CONFIG_GENERIC_MMC
  450. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  451. #endif
  452. #define CONFIG_USB_EHCI /* USB */
  453. #ifdef CONFIG_USB_EHCI
  454. #define CONFIG_CMD_USB
  455. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  456. #define CONFIG_USB_EHCI_FSL
  457. #define CONFIG_USB_STORAGE
  458. #define CONFIG_HAS_FSL_DR_USB
  459. #endif
  460. /*
  461. * Environment
  462. */
  463. #if defined(CONFIG_RAMBOOT_SDCARD)
  464. #define CONFIG_ENV_IS_IN_MMC
  465. #define CONFIG_FSL_FIXED_MMC_LOCATION
  466. #define CONFIG_SYS_MMC_ENV_DEV 0
  467. #define CONFIG_ENV_SIZE 0x2000
  468. #elif defined(CONFIG_RAMBOOT_SPIFLASH)
  469. #define CONFIG_ENV_IS_IN_SPI_FLASH
  470. #define CONFIG_ENV_SPI_BUS 0
  471. #define CONFIG_ENV_SPI_CS 0
  472. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  473. #define CONFIG_ENV_SPI_MODE 0
  474. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  475. #define CONFIG_ENV_SECT_SIZE 0x10000
  476. #define CONFIG_ENV_SIZE 0x2000
  477. #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
  478. #define CONFIG_ENV_IS_IN_NAND
  479. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  480. #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
  481. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
  482. #elif defined(CONFIG_SYS_RAMBOOT)
  483. #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
  484. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  485. #define CONFIG_ENV_SIZE 0x2000
  486. #else
  487. #define CONFIG_ENV_IS_IN_FLASH
  488. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  489. #define CONFIG_ENV_SIZE 0x2000
  490. #define CONFIG_ENV_SECT_SIZE 0x20000
  491. #endif
  492. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  493. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  494. /*
  495. * Command line configuration.
  496. */
  497. #include <config_cmd_default.h>
  498. #define CONFIG_CMD_DATE
  499. #define CONFIG_CMD_DHCP
  500. #define CONFIG_CMD_ELF
  501. #define CONFIG_CMD_ERRATA
  502. #define CONFIG_CMD_I2C
  503. #define CONFIG_CMD_IRQ
  504. #define CONFIG_CMD_MII
  505. #define CONFIG_CMD_PING
  506. #define CONFIG_CMD_SETEXPR
  507. #define CONFIG_CMD_REGINFO
  508. #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
  509. #define CONFIG_CMD_EXT2
  510. #define CONFIG_CMD_FAT
  511. #define CONFIG_DOS_PARTITION
  512. #endif
  513. /*
  514. * Miscellaneous configurable options
  515. */
  516. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  517. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  518. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  519. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  520. #if defined(CONFIG_CMD_KGDB)
  521. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  522. #else
  523. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  524. #endif
  525. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  526. /* Print Buffer Size */
  527. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  528. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  529. /*
  530. * For booting Linux, the board info and command line data
  531. * have to be in the first 64 MB of memory, since this is
  532. * the maximum mapped by the Linux kernel during initialization.
  533. */
  534. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
  535. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  536. #if defined(CONFIG_CMD_KGDB)
  537. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  538. #endif
  539. /*
  540. * Environment Configuration
  541. */
  542. #if defined(CONFIG_TSEC_ENET)
  543. #define CONFIG_HAS_ETH0
  544. #define CONFIG_HAS_ETH1
  545. #endif
  546. #define CONFIG_HOSTNAME BSC9132qds
  547. #define CONFIG_ROOTPATH "/opt/nfsroot"
  548. #define CONFIG_BOOTFILE "uImage"
  549. #define CONFIG_UBOOTPATH "u-boot.bin"
  550. #define CONFIG_BAUDRATE 115200
  551. #ifdef CONFIG_SDCARD
  552. #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
  553. #else
  554. #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
  555. #endif
  556. #define CONFIG_EXTRA_ENV_SETTINGS \
  557. "netdev=eth0\0" \
  558. "uboot=" CONFIG_UBOOTPATH "\0" \
  559. "loadaddr=1000000\0" \
  560. "bootfile=uImage\0" \
  561. "consoledev=ttyS0\0" \
  562. "ramdiskaddr=2000000\0" \
  563. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  564. "fdtaddr=c00000\0" \
  565. "fdtfile=bsc9132qds.dtb\0" \
  566. "bdev=sda1\0" \
  567. CONFIG_DEF_HWCONFIG\
  568. "othbootargs=mem=880M ramdisk_size=600000 " \
  569. "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
  570. "isolcpus=0\0" \
  571. "usbext2boot=setenv bootargs root=/dev/ram rw " \
  572. "console=$consoledev,$baudrate $othbootargs; " \
  573. "usb start;" \
  574. "ext2load usb 0:4 $loadaddr $bootfile;" \
  575. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  576. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  577. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  578. "debug_halt_off=mw ff7e0e30 0xf0000000;"
  579. #define CONFIG_NFSBOOTCOMMAND \
  580. "setenv bootargs root=/dev/nfs rw " \
  581. "nfsroot=$serverip:$rootpath " \
  582. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  583. "console=$consoledev,$baudrate $othbootargs;" \
  584. "tftp $loadaddr $bootfile;" \
  585. "tftp $fdtaddr $fdtfile;" \
  586. "bootm $loadaddr - $fdtaddr"
  587. #define CONFIG_HDBOOT \
  588. "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  589. "console=$consoledev,$baudrate $othbootargs;" \
  590. "usb start;" \
  591. "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  592. "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  593. "bootm $loadaddr - $fdtaddr"
  594. #define CONFIG_RAMBOOTCOMMAND \
  595. "setenv bootargs root=/dev/ram rw " \
  596. "console=$consoledev,$baudrate $othbootargs; " \
  597. "tftp $ramdiskaddr $ramdiskfile;" \
  598. "tftp $loadaddr $bootfile;" \
  599. "tftp $fdtaddr $fdtfile;" \
  600. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  601. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  602. #include <asm/fsl_secure_boot.h>
  603. #endif /* __CONFIG_H */