B4860QDS.h 29 KB

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  1. /*
  2. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #define CONFIG_SYS_GENERIC_BOARD
  9. #define CONFIG_DISPLAY_BOARDINFO
  10. /*
  11. * B4860 QDS board configuration file
  12. */
  13. #define CONFIG_B4860QDS
  14. #define CONFIG_PHYS_64BIT
  15. #ifdef CONFIG_RAMBOOT_PBL
  16. #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  17. #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  18. #ifndef CONFIG_NAND
  19. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  20. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  21. #else
  22. #define CONFIG_SPL 1
  23. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  24. #define CONFIG_SPL_ENV_SUPPORT
  25. #define CONFIG_SPL_SERIAL_SUPPORT
  26. #define CONFIG_SPL_FLUSH_IMAGE
  27. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  28. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  29. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  30. #define CONFIG_SPL_I2C_SUPPORT
  31. #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  32. #define CONFIG_FSL_LAW /* Use common FSL init code */
  33. #define CONFIG_SYS_TEXT_BASE 0x00201000
  34. #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
  35. #define CONFIG_SPL_PAD_TO 0x40000
  36. #define CONFIG_SPL_MAX_SIZE 0x28000
  37. #define RESET_VECTOR_OFFSET 0x27FFC
  38. #define BOOT_PAGE_OFFSET 0x27000
  39. #define CONFIG_SPL_NAND_SUPPORT
  40. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  41. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  42. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  43. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  44. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  45. #define CONFIG_SPL_NAND_BOOT
  46. #ifdef CONFIG_SPL_BUILD
  47. #define CONFIG_SPL_SKIP_RELOCATE
  48. #define CONFIG_SPL_COMMON_INIT_DDR
  49. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  50. #define CONFIG_SYS_NO_FLASH
  51. #endif
  52. #endif
  53. #endif
  54. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  55. /* Set 1M boot space */
  56. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  57. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  58. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  59. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  60. #define CONFIG_SYS_NO_FLASH
  61. #endif
  62. /* High Level Configuration Options */
  63. #define CONFIG_BOOKE
  64. #define CONFIG_E500 /* BOOKE e500 family */
  65. #define CONFIG_E500MC /* BOOKE e500mc family */
  66. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  67. #define CONFIG_MP /* support multiple processors */
  68. #ifndef CONFIG_SYS_TEXT_BASE
  69. #define CONFIG_SYS_TEXT_BASE 0xeff40000
  70. #endif
  71. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  72. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  73. #endif
  74. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  75. #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
  76. #define CONFIG_FSL_IFC /* Enable IFC Support */
  77. #define CONFIG_PCI /* Enable PCI/PCIE */
  78. #define CONFIG_PCIE1 /* PCIE controler 1 */
  79. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  80. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  81. #ifndef CONFIG_PPC_B4420
  82. #define CONFIG_SYS_SRIO
  83. #define CONFIG_SRIO1 /* SRIO port 1 */
  84. #define CONFIG_SRIO2 /* SRIO port 2 */
  85. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  86. #endif
  87. #define CONFIG_FSL_LAW /* Use common FSL init code */
  88. /* I2C bus multiplexer */
  89. #define I2C_MUX_PCA_ADDR 0x77
  90. /* VSC Crossbar switches */
  91. #define CONFIG_VSC_CROSSBAR
  92. #define I2C_CH_DEFAULT 0x8
  93. #define I2C_CH_VSC3316 0xc
  94. #define I2C_CH_VSC3308 0xd
  95. #define VSC3316_TX_ADDRESS 0x70
  96. #define VSC3316_RX_ADDRESS 0x71
  97. #define VSC3308_TX_ADDRESS 0x02
  98. #define VSC3308_RX_ADDRESS 0x03
  99. /* IDT clock synthesizers */
  100. #define CONFIG_IDT8T49N222A
  101. #define I2C_CH_IDT 0x9
  102. #define IDT_SERDES1_ADDRESS 0x6E
  103. #define IDT_SERDES2_ADDRESS 0x6C
  104. /* Voltage monitor on channel 2*/
  105. #define I2C_MUX_CH_VOL_MONITOR 0xa
  106. #define I2C_VOL_MONITOR_ADDR 0x40
  107. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  108. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  109. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  110. #define CONFIG_ZM7300
  111. #define I2C_MUX_CH_DPM 0xa
  112. #define I2C_DPM_ADDR 0x28
  113. #define CONFIG_ENV_OVERWRITE
  114. #ifdef CONFIG_SYS_NO_FLASH
  115. #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
  116. #define CONFIG_ENV_IS_NOWHERE
  117. #endif
  118. #else
  119. #define CONFIG_FLASH_CFI_DRIVER
  120. #define CONFIG_SYS_FLASH_CFI
  121. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  122. #endif
  123. #if defined(CONFIG_SPIFLASH)
  124. #define CONFIG_SYS_EXTRA_ENV_RELOC
  125. #define CONFIG_ENV_IS_IN_SPI_FLASH
  126. #define CONFIG_ENV_SPI_BUS 0
  127. #define CONFIG_ENV_SPI_CS 0
  128. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  129. #define CONFIG_ENV_SPI_MODE 0
  130. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  131. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  132. #define CONFIG_ENV_SECT_SIZE 0x10000
  133. #elif defined(CONFIG_SDCARD)
  134. #define CONFIG_SYS_EXTRA_ENV_RELOC
  135. #define CONFIG_ENV_IS_IN_MMC
  136. #define CONFIG_SYS_MMC_ENV_DEV 0
  137. #define CONFIG_ENV_SIZE 0x2000
  138. #define CONFIG_ENV_OFFSET (512 * 1097)
  139. #elif defined(CONFIG_NAND)
  140. #define CONFIG_SYS_EXTRA_ENV_RELOC
  141. #define CONFIG_ENV_IS_IN_NAND
  142. #define CONFIG_ENV_SIZE 0x2000
  143. #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  144. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  145. #define CONFIG_ENV_IS_IN_REMOTE
  146. #define CONFIG_ENV_ADDR 0xffe20000
  147. #define CONFIG_ENV_SIZE 0x2000
  148. #elif defined(CONFIG_ENV_IS_NOWHERE)
  149. #define CONFIG_ENV_SIZE 0x2000
  150. #else
  151. #define CONFIG_ENV_IS_IN_FLASH
  152. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  153. #define CONFIG_ENV_SIZE 0x2000
  154. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  155. #endif
  156. #ifndef __ASSEMBLY__
  157. unsigned long get_board_sys_clk(void);
  158. unsigned long get_board_ddr_clk(void);
  159. #endif
  160. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  161. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  162. /*
  163. * These can be toggled for performance analysis, otherwise use default.
  164. */
  165. #define CONFIG_SYS_CACHE_STASHING
  166. #define CONFIG_BTB /* toggle branch predition */
  167. #define CONFIG_DDR_ECC
  168. #ifdef CONFIG_DDR_ECC
  169. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  170. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  171. #endif
  172. #define CONFIG_ENABLE_36BIT_PHYS
  173. #ifdef CONFIG_PHYS_64BIT
  174. #define CONFIG_ADDR_MAP
  175. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  176. #endif
  177. #if 0
  178. #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
  179. #endif
  180. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  181. #define CONFIG_SYS_MEMTEST_END 0x00400000
  182. #define CONFIG_SYS_ALT_MEMTEST
  183. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  184. /*
  185. * Config the L3 Cache as L3 SRAM
  186. */
  187. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  188. #define CONFIG_SYS_L3_SIZE 256 << 10
  189. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  190. #ifdef CONFIG_NAND
  191. #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  192. #endif
  193. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  194. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  195. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  196. #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
  197. #ifdef CONFIG_PHYS_64BIT
  198. #define CONFIG_SYS_DCSRBAR 0xf0000000
  199. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  200. #endif
  201. /* EEPROM */
  202. #define CONFIG_SYS_I2C_EEPROM_NXID
  203. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  204. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  205. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  206. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  207. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  208. /*
  209. * DDR Setup
  210. */
  211. #define CONFIG_VERY_BIG_RAM
  212. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  213. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  214. /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
  215. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  216. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  217. #define CONFIG_DDR_SPD
  218. #define CONFIG_SYS_DDR_RAW_TIMING
  219. #define CONFIG_SYS_FSL_DDR3
  220. #ifndef CONFIG_SPL_BUILD
  221. #define CONFIG_FSL_DDR_INTERACTIVE
  222. #endif
  223. #define CONFIG_SYS_SPD_BUS_NUM 0
  224. #define SPD_EEPROM_ADDRESS1 0x51
  225. #define SPD_EEPROM_ADDRESS2 0x53
  226. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  227. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  228. /*
  229. * IFC Definitions
  230. */
  231. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  232. #ifdef CONFIG_PHYS_64BIT
  233. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  234. #else
  235. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  236. #endif
  237. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  238. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  239. + 0x8000000) | \
  240. CSPR_PORT_SIZE_16 | \
  241. CSPR_MSEL_NOR | \
  242. CSPR_V)
  243. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  244. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  245. CSPR_PORT_SIZE_16 | \
  246. CSPR_MSEL_NOR | \
  247. CSPR_V)
  248. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  249. /* NOR Flash Timing Params */
  250. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
  251. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
  252. FTIM0_NOR_TEADC(0x04) | \
  253. FTIM0_NOR_TEAHC(0x20))
  254. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  255. FTIM1_NOR_TRAD_NOR(0x1A) |\
  256. FTIM1_NOR_TSEQRAD_NOR(0x13))
  257. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
  258. FTIM2_NOR_TCH(0x0E) | \
  259. FTIM2_NOR_TWPH(0x0E) | \
  260. FTIM2_NOR_TWP(0x1c))
  261. #define CONFIG_SYS_NOR_FTIM3 0x0
  262. #define CONFIG_SYS_FLASH_QUIET_TEST
  263. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  264. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  265. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  266. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  267. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  268. #define CONFIG_SYS_FLASH_EMPTY_INFO
  269. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  270. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  271. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  272. #define CONFIG_FSL_QIXIS_V2
  273. #define QIXIS_BASE 0xffdf0000
  274. #ifdef CONFIG_PHYS_64BIT
  275. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  276. #else
  277. #define QIXIS_BASE_PHYS QIXIS_BASE
  278. #endif
  279. #define QIXIS_LBMAP_SWITCH 0x01
  280. #define QIXIS_LBMAP_MASK 0x0f
  281. #define QIXIS_LBMAP_SHIFT 0
  282. #define QIXIS_LBMAP_DFLTBANK 0x00
  283. #define QIXIS_LBMAP_ALTBANK 0x02
  284. #define QIXIS_RST_CTL_RESET 0x31
  285. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  286. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  287. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  288. #define CONFIG_SYS_CSPR3_EXT (0xf)
  289. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  290. | CSPR_PORT_SIZE_8 \
  291. | CSPR_MSEL_GPCM \
  292. | CSPR_V)
  293. #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
  294. #define CONFIG_SYS_CSOR3 0x0
  295. /* QIXIS Timing parameters for IFC CS3 */
  296. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  297. FTIM0_GPCM_TEADC(0x0e) | \
  298. FTIM0_GPCM_TEAHC(0x0e))
  299. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  300. FTIM1_GPCM_TRAD(0x1f))
  301. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  302. FTIM2_GPCM_TCH(0x8) | \
  303. FTIM2_GPCM_TWP(0x1f))
  304. #define CONFIG_SYS_CS3_FTIM3 0x0
  305. /* NAND Flash on IFC */
  306. #define CONFIG_NAND_FSL_IFC
  307. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  308. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  309. #define CONFIG_SYS_NAND_BASE 0xff800000
  310. #ifdef CONFIG_PHYS_64BIT
  311. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  312. #else
  313. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  314. #endif
  315. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  316. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  317. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  318. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  319. | CSPR_V)
  320. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  321. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  322. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  323. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  324. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  325. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  326. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  327. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  328. #define CONFIG_SYS_NAND_ONFI_DETECTION
  329. /* ONFI NAND Flash mode0 Timing Params */
  330. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  331. FTIM0_NAND_TWP(0x18) | \
  332. FTIM0_NAND_TWCHT(0x07) | \
  333. FTIM0_NAND_TWH(0x0a))
  334. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  335. FTIM1_NAND_TWBE(0x39) | \
  336. FTIM1_NAND_TRR(0x0e) | \
  337. FTIM1_NAND_TRP(0x18))
  338. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  339. FTIM2_NAND_TREH(0x0a) | \
  340. FTIM2_NAND_TWHRE(0x1e))
  341. #define CONFIG_SYS_NAND_FTIM3 0x0
  342. #define CONFIG_SYS_NAND_DDR_LAW 11
  343. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  344. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  345. #define CONFIG_MTD_NAND_VERIFY_WRITE
  346. #define CONFIG_CMD_NAND
  347. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  348. #if defined(CONFIG_NAND)
  349. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  350. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  351. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  352. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  353. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  354. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  355. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  356. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  357. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  358. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
  359. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  360. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  361. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  362. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  363. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  364. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  365. #else
  366. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  367. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  368. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  369. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  370. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  371. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  372. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  373. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  374. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  375. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  376. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  377. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  378. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  379. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  380. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  381. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  382. #endif
  383. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  384. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  385. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  386. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  387. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  388. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  389. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  390. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  391. #ifdef CONFIG_SPL_BUILD
  392. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  393. #else
  394. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  395. #endif
  396. #if defined(CONFIG_RAMBOOT_PBL)
  397. #define CONFIG_SYS_RAMBOOT
  398. #endif
  399. #define CONFIG_BOARD_EARLY_INIT_R
  400. #define CONFIG_MISC_INIT_R
  401. #define CONFIG_HWCONFIG
  402. /* define to use L1 as initial stack */
  403. #define CONFIG_L1_INIT_RAM
  404. #define CONFIG_SYS_INIT_RAM_LOCK
  405. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  406. #ifdef CONFIG_PHYS_64BIT
  407. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  408. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
  409. /* The assembler doesn't like typecast */
  410. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  411. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  412. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  413. #else
  414. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
  415. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  416. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  417. #endif
  418. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  419. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  420. GENERATED_GBL_DATA_SIZE)
  421. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  422. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  423. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  424. /* Serial Port - controlled on board with jumper J8
  425. * open - index 2
  426. * shorted - index 1
  427. */
  428. #define CONFIG_CONS_INDEX 1
  429. #define CONFIG_SYS_NS16550
  430. #define CONFIG_SYS_NS16550_SERIAL
  431. #define CONFIG_SYS_NS16550_REG_SIZE 1
  432. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  433. #define CONFIG_SYS_BAUDRATE_TABLE \
  434. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  435. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  436. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  437. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  438. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  439. #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
  440. #ifndef CONFIG_SPL_BUILD
  441. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
  442. #endif
  443. /* Use the HUSH parser */
  444. #define CONFIG_SYS_HUSH_PARSER
  445. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  446. /* pass open firmware flat tree */
  447. #define CONFIG_OF_LIBFDT
  448. #define CONFIG_OF_BOARD_SETUP
  449. #define CONFIG_OF_STDOUT_VIA_ALIAS
  450. /* new uImage format support */
  451. #define CONFIG_FIT
  452. #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  453. /* I2C */
  454. #define CONFIG_SYS_I2C
  455. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  456. #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
  457. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  458. #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
  459. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  460. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  461. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
  462. /*
  463. * RTC configuration
  464. */
  465. #define RTC
  466. #define CONFIG_RTC_DS3231 1
  467. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  468. /*
  469. * RapidIO
  470. */
  471. #ifdef CONFIG_SYS_SRIO
  472. #ifdef CONFIG_SRIO1
  473. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  474. #ifdef CONFIG_PHYS_64BIT
  475. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  476. #else
  477. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
  478. #endif
  479. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  480. #endif
  481. #ifdef CONFIG_SRIO2
  482. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  483. #ifdef CONFIG_PHYS_64BIT
  484. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  485. #else
  486. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
  487. #endif
  488. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  489. #endif
  490. #endif
  491. /*
  492. * for slave u-boot IMAGE instored in master memory space,
  493. * PHYS must be aligned based on the SIZE
  494. */
  495. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  496. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  497. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  498. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  499. /*
  500. * for slave UCODE and ENV instored in master memory space,
  501. * PHYS must be aligned based on the SIZE
  502. */
  503. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  504. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  505. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  506. /* slave core release by master*/
  507. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  508. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  509. /*
  510. * SRIO_PCIE_BOOT - SLAVE
  511. */
  512. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  513. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  514. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  515. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  516. #endif
  517. /*
  518. * eSPI - Enhanced SPI
  519. */
  520. #define CONFIG_FSL_ESPI
  521. #define CONFIG_SPI_FLASH
  522. #define CONFIG_SPI_FLASH_SST
  523. #define CONFIG_CMD_SF
  524. #define CONFIG_SF_DEFAULT_SPEED 10000000
  525. #define CONFIG_SF_DEFAULT_MODE 0
  526. /*
  527. * MAPLE
  528. */
  529. #ifdef CONFIG_PHYS_64BIT
  530. #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
  531. #else
  532. #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
  533. #endif
  534. /*
  535. * General PCI
  536. * Memory space is mapped 1-1, but I/O space must start from 0.
  537. */
  538. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  539. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  540. #ifdef CONFIG_PHYS_64BIT
  541. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  542. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  543. #else
  544. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  545. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  546. #endif
  547. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  548. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  549. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  550. #ifdef CONFIG_PHYS_64BIT
  551. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  552. #else
  553. #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
  554. #endif
  555. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  556. /* Qman/Bman */
  557. #ifndef CONFIG_NOBQFMAN
  558. #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
  559. #define CONFIG_SYS_BMAN_NUM_PORTALS 25
  560. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  561. #ifdef CONFIG_PHYS_64BIT
  562. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  563. #else
  564. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  565. #endif
  566. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  567. #define CONFIG_SYS_QMAN_NUM_PORTALS 25
  568. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  569. #ifdef CONFIG_PHYS_64BIT
  570. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  571. #else
  572. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  573. #endif
  574. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  575. #define CONFIG_SYS_DPAA_FMAN
  576. #define CONFIG_SYS_DPAA_RMAN
  577. /* Default address of microcode for the Linux Fman driver */
  578. #if defined(CONFIG_SPIFLASH)
  579. /*
  580. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  581. * env, so we got 0x110000.
  582. */
  583. #define CONFIG_SYS_QE_FW_IN_SPIFLASH
  584. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  585. #elif defined(CONFIG_SDCARD)
  586. /*
  587. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  588. * about 545KB (1089 blocks), Env is stored after the image, and the env size is
  589. * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
  590. */
  591. #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  592. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
  593. #elif defined(CONFIG_NAND)
  594. #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  595. #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
  596. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  597. /*
  598. * Slave has no ucode locally, it can fetch this from remote. When implementing
  599. * in two corenet boards, slave's ucode could be stored in master's memory
  600. * space, the address can be mapped from slave TLB->slave LAW->
  601. * slave SRIO or PCIE outbound window->master inbound window->
  602. * master LAW->the ucode address in master's memory space.
  603. */
  604. #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
  605. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  606. #else
  607. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  608. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  609. #endif
  610. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  611. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  612. #endif /* CONFIG_NOBQFMAN */
  613. #ifdef CONFIG_SYS_DPAA_FMAN
  614. #define CONFIG_FMAN_ENET
  615. #define CONFIG_PHYLIB_10G
  616. #define CONFIG_PHY_VITESSE
  617. #define CONFIG_PHY_TERANETICS
  618. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  619. #define SGMII_CARD_PORT2_PHY_ADDR 0x10
  620. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  621. #define SGMII_CARD_PORT4_PHY_ADDR 0x11
  622. #endif
  623. #ifdef CONFIG_PCI
  624. #define CONFIG_PCI_INDIRECT_BRIDGE
  625. #define CONFIG_NET_MULTI
  626. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  627. #define CONFIG_E1000
  628. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  629. #define CONFIG_DOS_PARTITION
  630. #endif /* CONFIG_PCI */
  631. #ifdef CONFIG_FMAN_ENET
  632. #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
  633. #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
  634. /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
  635. #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
  636. #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
  637. #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
  638. #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
  639. #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
  640. #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
  641. #define CONFIG_MII /* MII PHY management */
  642. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  643. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  644. #endif
  645. /*
  646. * Environment
  647. */
  648. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  649. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  650. /*
  651. * Command line configuration.
  652. */
  653. #include <config_cmd_default.h>
  654. #define CONFIG_CMD_DATE
  655. #define CONFIG_CMD_DHCP
  656. #define CONFIG_CMD_EEPROM
  657. #define CONFIG_CMD_ELF
  658. #define CONFIG_CMD_ERRATA
  659. #define CONFIG_CMD_GREPENV
  660. #define CONFIG_CMD_IRQ
  661. #define CONFIG_CMD_I2C
  662. #define CONFIG_CMD_MII
  663. #define CONFIG_CMD_PING
  664. #define CONFIG_CMD_REGINFO
  665. #define CONFIG_CMD_SETEXPR
  666. #ifdef CONFIG_PCI
  667. #define CONFIG_CMD_PCI
  668. #define CONFIG_CMD_NET
  669. #endif
  670. /*
  671. * USB
  672. */
  673. #define CONFIG_HAS_FSL_DR_USB
  674. #ifdef CONFIG_HAS_FSL_DR_USB
  675. #define CONFIG_USB_EHCI
  676. #ifdef CONFIG_USB_EHCI
  677. #define CONFIG_CMD_USB
  678. #define CONFIG_USB_STORAGE
  679. #define CONFIG_USB_EHCI_FSL
  680. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  681. #define CONFIG_CMD_EXT2
  682. #endif
  683. #endif
  684. /*
  685. * Miscellaneous configurable options
  686. */
  687. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  688. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  689. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  690. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  691. #ifdef CONFIG_CMD_KGDB
  692. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  693. #else
  694. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  695. #endif
  696. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  697. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  698. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  699. /*
  700. * For booting Linux, the board info and command line data
  701. * have to be in the first 64 MB of memory, since this is
  702. * the maximum mapped by the Linux kernel during initialization.
  703. */
  704. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  705. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  706. #ifdef CONFIG_CMD_KGDB
  707. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  708. #endif
  709. /*
  710. * Environment Configuration
  711. */
  712. #define CONFIG_ROOTPATH "/opt/nfsroot"
  713. #define CONFIG_BOOTFILE "uImage"
  714. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  715. /* default location for tftp and bootm */
  716. #define CONFIG_LOADADDR 1000000
  717. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  718. #define CONFIG_BAUDRATE 115200
  719. #define __USB_PHY_TYPE ulpi
  720. #define CONFIG_EXTRA_ENV_SETTINGS \
  721. "hwconfig=fsl_ddr:ctlr_intlv=null," \
  722. "bank_intlv=cs0_cs1;" \
  723. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  724. "netdev=eth0\0" \
  725. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  726. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  727. "tftpflash=tftpboot $loadaddr $uboot && " \
  728. "protect off $ubootaddr +$filesize && " \
  729. "erase $ubootaddr +$filesize && " \
  730. "cp.b $loadaddr $ubootaddr $filesize && " \
  731. "protect on $ubootaddr +$filesize && " \
  732. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  733. "consoledev=ttyS0\0" \
  734. "ramdiskaddr=2000000\0" \
  735. "ramdiskfile=b4860qds/ramdisk.uboot\0" \
  736. "fdtaddr=c00000\0" \
  737. "fdtfile=b4860qds/b4860qds.dtb\0" \
  738. "bdev=sda3\0"
  739. /* For emulation this causes u-boot to jump to the start of the proof point
  740. app code automatically */
  741. #define CONFIG_PROOF_POINTS \
  742. "setenv bootargs root=/dev/$bdev rw " \
  743. "console=$consoledev,$baudrate $othbootargs;" \
  744. "cpu 1 release 0x29000000 - - -;" \
  745. "cpu 2 release 0x29000000 - - -;" \
  746. "cpu 3 release 0x29000000 - - -;" \
  747. "cpu 4 release 0x29000000 - - -;" \
  748. "cpu 5 release 0x29000000 - - -;" \
  749. "cpu 6 release 0x29000000 - - -;" \
  750. "cpu 7 release 0x29000000 - - -;" \
  751. "go 0x29000000"
  752. #define CONFIG_HVBOOT \
  753. "setenv bootargs config-addr=0x60000000; " \
  754. "bootm 0x01000000 - 0x00f00000"
  755. #define CONFIG_ALU \
  756. "setenv bootargs root=/dev/$bdev rw " \
  757. "console=$consoledev,$baudrate $othbootargs;" \
  758. "cpu 1 release 0x01000000 - - -;" \
  759. "cpu 2 release 0x01000000 - - -;" \
  760. "cpu 3 release 0x01000000 - - -;" \
  761. "cpu 4 release 0x01000000 - - -;" \
  762. "cpu 5 release 0x01000000 - - -;" \
  763. "cpu 6 release 0x01000000 - - -;" \
  764. "cpu 7 release 0x01000000 - - -;" \
  765. "go 0x01000000"
  766. #define CONFIG_LINUX \
  767. "setenv bootargs root=/dev/ram rw " \
  768. "console=$consoledev,$baudrate $othbootargs;" \
  769. "setenv ramdiskaddr 0x02000000;" \
  770. "setenv fdtaddr 0x00c00000;" \
  771. "setenv loadaddr 0x1000000;" \
  772. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  773. #define CONFIG_HDBOOT \
  774. "setenv bootargs root=/dev/$bdev rw " \
  775. "console=$consoledev,$baudrate $othbootargs;" \
  776. "tftp $loadaddr $bootfile;" \
  777. "tftp $fdtaddr $fdtfile;" \
  778. "bootm $loadaddr - $fdtaddr"
  779. #define CONFIG_NFSBOOTCOMMAND \
  780. "setenv bootargs root=/dev/nfs rw " \
  781. "nfsroot=$serverip:$rootpath " \
  782. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  783. "console=$consoledev,$baudrate $othbootargs;" \
  784. "tftp $loadaddr $bootfile;" \
  785. "tftp $fdtaddr $fdtfile;" \
  786. "bootm $loadaddr - $fdtaddr"
  787. #define CONFIG_RAMBOOTCOMMAND \
  788. "setenv bootargs root=/dev/ram rw " \
  789. "console=$consoledev,$baudrate $othbootargs;" \
  790. "tftp $ramdiskaddr $ramdiskfile;" \
  791. "tftp $loadaddr $bootfile;" \
  792. "tftp $fdtaddr $fdtfile;" \
  793. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  794. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  795. #include <asm/fsl_secure_boot.h>
  796. #endif /* __CONFIG_H */