tegra20_sflash.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2010-2013 NVIDIA Corporation
  4. * With help from the mpc8xxx SPI driver
  5. * With more help from omap3_spi SPI driver
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <asm/io.h>
  11. #include <asm/gpio.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/pinmux.h>
  14. #include <asm/arch-tegra/clk_rst.h>
  15. #include <spi.h>
  16. #include <fdtdec.h>
  17. #include "tegra_spi.h"
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define SPI_CMD_GO BIT(30)
  20. #define SPI_CMD_ACTIVE_SCLK_SHIFT 26
  21. #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
  22. #define SPI_CMD_CK_SDA BIT(21)
  23. #define SPI_CMD_ACTIVE_SDA_SHIFT 18
  24. #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
  25. #define SPI_CMD_CS_POL BIT(16)
  26. #define SPI_CMD_TXEN BIT(15)
  27. #define SPI_CMD_RXEN BIT(14)
  28. #define SPI_CMD_CS_VAL BIT(13)
  29. #define SPI_CMD_CS_SOFT BIT(12)
  30. #define SPI_CMD_CS_DELAY BIT(9)
  31. #define SPI_CMD_CS3_EN BIT(8)
  32. #define SPI_CMD_CS2_EN BIT(7)
  33. #define SPI_CMD_CS1_EN BIT(6)
  34. #define SPI_CMD_CS0_EN BIT(5)
  35. #define SPI_CMD_BIT_LENGTH BIT(4)
  36. #define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
  37. #define SPI_STAT_BSY BIT(31)
  38. #define SPI_STAT_RDY BIT(30)
  39. #define SPI_STAT_RXF_FLUSH BIT(29)
  40. #define SPI_STAT_TXF_FLUSH BIT(28)
  41. #define SPI_STAT_RXF_UNR BIT(27)
  42. #define SPI_STAT_TXF_OVF BIT(26)
  43. #define SPI_STAT_RXF_EMPTY BIT(25)
  44. #define SPI_STAT_RXF_FULL BIT(24)
  45. #define SPI_STAT_TXF_EMPTY BIT(23)
  46. #define SPI_STAT_TXF_FULL BIT(22)
  47. #define SPI_STAT_SEL_TXRX_N BIT(16)
  48. #define SPI_STAT_CUR_BLKCNT BIT(15)
  49. #define SPI_TIMEOUT 1000
  50. #define TEGRA_SPI_MAX_FREQ 52000000
  51. struct spi_regs {
  52. u32 command; /* SPI_COMMAND_0 register */
  53. u32 status; /* SPI_STATUS_0 register */
  54. u32 rx_cmp; /* SPI_RX_CMP_0 register */
  55. u32 dma_ctl; /* SPI_DMA_CTL_0 register */
  56. u32 tx_fifo; /* SPI_TX_FIFO_0 register */
  57. u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
  58. u32 rx_fifo; /* SPI_RX_FIFO_0 register */
  59. };
  60. struct tegra20_sflash_priv {
  61. struct spi_regs *regs;
  62. unsigned int freq;
  63. unsigned int mode;
  64. int periph_id;
  65. int valid;
  66. int last_transaction_us;
  67. };
  68. int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
  69. struct spi_cs_info *info)
  70. {
  71. /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
  72. if (cs != 0)
  73. return -EINVAL;
  74. else
  75. return 0;
  76. }
  77. static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
  78. {
  79. struct tegra_spi_platdata *plat = bus->platdata;
  80. const void *blob = gd->fdt_blob;
  81. int node = dev_of_offset(bus);
  82. plat->base = devfdt_get_addr(bus);
  83. plat->periph_id = clock_decode_periph_id(bus);
  84. if (plat->periph_id == PERIPH_ID_NONE) {
  85. debug("%s: could not decode periph id %d\n", __func__,
  86. plat->periph_id);
  87. return -FDT_ERR_NOTFOUND;
  88. }
  89. /* Use 500KHz as a suitable default */
  90. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  91. 500000);
  92. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  93. "spi-deactivate-delay", 0);
  94. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  95. __func__, plat->base, plat->periph_id, plat->frequency,
  96. plat->deactivate_delay_us);
  97. return 0;
  98. }
  99. static int tegra20_sflash_probe(struct udevice *bus)
  100. {
  101. struct tegra_spi_platdata *plat = dev_get_platdata(bus);
  102. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  103. priv->regs = (struct spi_regs *)plat->base;
  104. priv->last_transaction_us = timer_get_us();
  105. priv->freq = plat->frequency;
  106. priv->periph_id = plat->periph_id;
  107. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  108. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  109. priv->freq);
  110. return 0;
  111. }
  112. static int tegra20_sflash_claim_bus(struct udevice *dev)
  113. {
  114. struct udevice *bus = dev->parent;
  115. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  116. struct spi_regs *regs = priv->regs;
  117. u32 reg;
  118. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  119. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  120. priv->freq);
  121. /* Clear stale status here */
  122. reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
  123. SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
  124. writel(reg, &regs->status);
  125. debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
  126. /*
  127. * Use sw-controlled CS, so we can clock in data after ReadID, etc.
  128. */
  129. reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
  130. if (priv->mode & 2)
  131. reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
  132. clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
  133. SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
  134. debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
  135. /*
  136. * SPI pins on Tegra20 are muxed - change pinmux later due to UART
  137. * issue.
  138. */
  139. pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
  140. pinmux_tristate_disable(PMUX_PINGRP_LSPI);
  141. pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
  142. return 0;
  143. }
  144. static void spi_cs_activate(struct udevice *dev)
  145. {
  146. struct udevice *bus = dev->parent;
  147. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  148. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  149. /* If it's too soon to do another transaction, wait */
  150. if (pdata->deactivate_delay_us &&
  151. priv->last_transaction_us) {
  152. ulong delay_us; /* The delay completed so far */
  153. delay_us = timer_get_us() - priv->last_transaction_us;
  154. if (delay_us < pdata->deactivate_delay_us)
  155. udelay(pdata->deactivate_delay_us - delay_us);
  156. }
  157. /* CS is negated on Tegra, so drive a 1 to get a 0 */
  158. setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
  159. }
  160. static void spi_cs_deactivate(struct udevice *dev)
  161. {
  162. struct udevice *bus = dev->parent;
  163. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  164. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  165. /* CS is negated on Tegra, so drive a 0 to get a 1 */
  166. clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
  167. /* Remember time of this transaction so we can honour the bus delay */
  168. if (pdata->deactivate_delay_us)
  169. priv->last_transaction_us = timer_get_us();
  170. }
  171. static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
  172. const void *data_out, void *data_in,
  173. unsigned long flags)
  174. {
  175. struct udevice *bus = dev->parent;
  176. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  177. struct spi_regs *regs = priv->regs;
  178. u32 reg, tmpdout, tmpdin = 0;
  179. const u8 *dout = data_out;
  180. u8 *din = data_in;
  181. int num_bytes;
  182. int ret;
  183. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  184. __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
  185. if (bitlen % 8)
  186. return -1;
  187. num_bytes = bitlen / 8;
  188. ret = 0;
  189. reg = readl(&regs->status);
  190. writel(reg, &regs->status); /* Clear all SPI events via R/W */
  191. debug("spi_xfer entry: STATUS = %08x\n", reg);
  192. reg = readl(&regs->command);
  193. reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
  194. writel(reg, &regs->command);
  195. debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
  196. if (flags & SPI_XFER_BEGIN)
  197. spi_cs_activate(dev);
  198. /* handle data in 32-bit chunks */
  199. while (num_bytes > 0) {
  200. int bytes;
  201. int is_read = 0;
  202. int tm, i;
  203. tmpdout = 0;
  204. bytes = (num_bytes > 4) ? 4 : num_bytes;
  205. if (dout != NULL) {
  206. for (i = 0; i < bytes; ++i)
  207. tmpdout = (tmpdout << 8) | dout[i];
  208. }
  209. num_bytes -= bytes;
  210. if (dout)
  211. dout += bytes;
  212. clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
  213. bytes * 8 - 1);
  214. writel(tmpdout, &regs->tx_fifo);
  215. setbits_le32(&regs->command, SPI_CMD_GO);
  216. /*
  217. * Wait for SPI transmit FIFO to empty, or to time out.
  218. * The RX FIFO status will be read and cleared last
  219. */
  220. for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
  221. u32 status;
  222. status = readl(&regs->status);
  223. /* We can exit when we've had both RX and TX activity */
  224. if (is_read && (status & SPI_STAT_TXF_EMPTY))
  225. break;
  226. if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
  227. SPI_STAT_RDY)
  228. tm++;
  229. else if (!(status & SPI_STAT_RXF_EMPTY)) {
  230. tmpdin = readl(&regs->rx_fifo);
  231. is_read = 1;
  232. /* swap bytes read in */
  233. if (din != NULL) {
  234. for (i = bytes - 1; i >= 0; --i) {
  235. din[i] = tmpdin & 0xff;
  236. tmpdin >>= 8;
  237. }
  238. din += bytes;
  239. }
  240. }
  241. }
  242. if (tm >= SPI_TIMEOUT)
  243. ret = tm;
  244. /* clear ACK RDY, etc. bits */
  245. writel(readl(&regs->status), &regs->status);
  246. }
  247. if (flags & SPI_XFER_END)
  248. spi_cs_deactivate(dev);
  249. debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
  250. tmpdin, readl(&regs->status));
  251. if (ret) {
  252. printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
  253. return -1;
  254. }
  255. return 0;
  256. }
  257. static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
  258. {
  259. struct tegra_spi_platdata *plat = bus->platdata;
  260. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  261. if (speed > plat->frequency)
  262. speed = plat->frequency;
  263. priv->freq = speed;
  264. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  265. return 0;
  266. }
  267. static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
  268. {
  269. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  270. priv->mode = mode;
  271. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  272. return 0;
  273. }
  274. static const struct dm_spi_ops tegra20_sflash_ops = {
  275. .claim_bus = tegra20_sflash_claim_bus,
  276. .xfer = tegra20_sflash_xfer,
  277. .set_speed = tegra20_sflash_set_speed,
  278. .set_mode = tegra20_sflash_set_mode,
  279. .cs_info = tegra20_sflash_cs_info,
  280. };
  281. static const struct udevice_id tegra20_sflash_ids[] = {
  282. { .compatible = "nvidia,tegra20-sflash" },
  283. { }
  284. };
  285. U_BOOT_DRIVER(tegra20_sflash) = {
  286. .name = "tegra20_sflash",
  287. .id = UCLASS_SPI,
  288. .of_match = tegra20_sflash_ids,
  289. .ops = &tegra20_sflash_ops,
  290. .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
  291. .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
  292. .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
  293. .probe = tegra20_sflash_probe,
  294. };