bcm63xx_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/drivers/spi/spi-bcm63xx.c:
  6. * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
  7. * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <spi.h>
  13. #include <reset.h>
  14. #include <wait_bit.h>
  15. #include <asm/io.h>
  16. /* BCM6348 SPI core */
  17. #define SPI_6348_CLK 0x06
  18. #define SPI_6348_CMD 0x00
  19. #define SPI_6348_CTL 0x40
  20. #define SPI_6348_CTL_SHIFT 6
  21. #define SPI_6348_FILL 0x07
  22. #define SPI_6348_IR_MASK 0x04
  23. #define SPI_6348_IR_STAT 0x02
  24. #define SPI_6348_RX 0x80
  25. #define SPI_6348_RX_SIZE 0x3f
  26. #define SPI_6348_TX 0x41
  27. #define SPI_6348_TX_SIZE 0x3f
  28. /* BCM6358 SPI core */
  29. #define SPI_6358_CLK 0x706
  30. #define SPI_6358_CMD 0x700
  31. #define SPI_6358_CTL 0x000
  32. #define SPI_6358_CTL_SHIFT 14
  33. #define SPI_6358_FILL 0x707
  34. #define SPI_6358_IR_MASK 0x702
  35. #define SPI_6358_IR_STAT 0x704
  36. #define SPI_6358_RX 0x400
  37. #define SPI_6358_RX_SIZE 0x220
  38. #define SPI_6358_TX 0x002
  39. #define SPI_6358_TX_SIZE 0x21e
  40. /* SPI Clock register */
  41. #define SPI_CLK_SHIFT 0
  42. #define SPI_CLK_20MHZ (0 << SPI_CLK_SHIFT)
  43. #define SPI_CLK_0_391MHZ (1 << SPI_CLK_SHIFT)
  44. #define SPI_CLK_0_781MHZ (2 << SPI_CLK_SHIFT)
  45. #define SPI_CLK_1_563MHZ (3 << SPI_CLK_SHIFT)
  46. #define SPI_CLK_3_125MHZ (4 << SPI_CLK_SHIFT)
  47. #define SPI_CLK_6_250MHZ (5 << SPI_CLK_SHIFT)
  48. #define SPI_CLK_12_50MHZ (6 << SPI_CLK_SHIFT)
  49. #define SPI_CLK_25MHZ (7 << SPI_CLK_SHIFT)
  50. #define SPI_CLK_MASK (7 << SPI_CLK_SHIFT)
  51. #define SPI_CLK_SSOFF_SHIFT 3
  52. #define SPI_CLK_SSOFF_2 (2 << SPI_CLK_SSOFF_SHIFT)
  53. #define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT)
  54. #define SPI_CLK_BSWAP_SHIFT 7
  55. #define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT)
  56. /* SPI Command register */
  57. #define SPI_CMD_OP_SHIFT 0
  58. #define SPI_CMD_OP_START (0x3 << SPI_CMD_OP_SHIFT)
  59. #define SPI_CMD_SLAVE_SHIFT 4
  60. #define SPI_CMD_SLAVE_MASK (0xf << SPI_CMD_SLAVE_SHIFT)
  61. #define SPI_CMD_PREPEND_SHIFT 8
  62. #define SPI_CMD_PREPEND_BYTES 0xf
  63. #define SPI_CMD_3WIRE_SHIFT 12
  64. #define SPI_CMD_3WIRE_MASK (1 << SPI_CMD_3WIRE_SHIFT)
  65. /* SPI Control register */
  66. #define SPI_CTL_TYPE_FD_RW 0
  67. #define SPI_CTL_TYPE_HD_W 1
  68. #define SPI_CTL_TYPE_HD_R 2
  69. /* SPI Interrupt registers */
  70. #define SPI_IR_DONE_SHIFT 0
  71. #define SPI_IR_DONE_MASK (1 << SPI_IR_DONE_SHIFT)
  72. #define SPI_IR_RXOVER_SHIFT 1
  73. #define SPI_IR_RXOVER_MASK (1 << SPI_IR_RXOVER_SHIFT)
  74. #define SPI_IR_TXUNDER_SHIFT 2
  75. #define SPI_IR_TXUNDER_MASK (1 << SPI_IR_TXUNDER_SHIFT)
  76. #define SPI_IR_TXOVER_SHIFT 3
  77. #define SPI_IR_TXOVER_MASK (1 << SPI_IR_TXOVER_SHIFT)
  78. #define SPI_IR_RXUNDER_SHIFT 4
  79. #define SPI_IR_RXUNDER_MASK (1 << SPI_IR_RXUNDER_SHIFT)
  80. #define SPI_IR_CLEAR_MASK (SPI_IR_DONE_MASK |\
  81. SPI_IR_RXOVER_MASK |\
  82. SPI_IR_TXUNDER_MASK |\
  83. SPI_IR_TXOVER_MASK |\
  84. SPI_IR_RXUNDER_MASK)
  85. enum bcm63xx_regs_spi {
  86. SPI_CLK,
  87. SPI_CMD,
  88. SPI_CTL,
  89. SPI_CTL_SHIFT,
  90. SPI_FILL,
  91. SPI_IR_MASK,
  92. SPI_IR_STAT,
  93. SPI_RX,
  94. SPI_RX_SIZE,
  95. SPI_TX,
  96. SPI_TX_SIZE,
  97. };
  98. struct bcm63xx_spi_priv {
  99. const unsigned long *regs;
  100. void __iomem *base;
  101. size_t tx_bytes;
  102. uint8_t num_cs;
  103. };
  104. #define SPI_CLK_CNT 8
  105. static const unsigned bcm63xx_spi_freq_table[SPI_CLK_CNT][2] = {
  106. { 25000000, SPI_CLK_25MHZ },
  107. { 20000000, SPI_CLK_20MHZ },
  108. { 12500000, SPI_CLK_12_50MHZ },
  109. { 6250000, SPI_CLK_6_250MHZ },
  110. { 3125000, SPI_CLK_3_125MHZ },
  111. { 1563000, SPI_CLK_1_563MHZ },
  112. { 781000, SPI_CLK_0_781MHZ },
  113. { 391000, SPI_CLK_0_391MHZ }
  114. };
  115. static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs,
  116. struct spi_cs_info *info)
  117. {
  118. struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  119. if (cs >= priv->num_cs) {
  120. printf("no cs %u\n", cs);
  121. return -EINVAL;
  122. }
  123. return 0;
  124. }
  125. static int bcm63xx_spi_set_mode(struct udevice *bus, uint mode)
  126. {
  127. struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  128. const unsigned long *regs = priv->regs;
  129. if (mode & SPI_LSB_FIRST)
  130. setbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
  131. else
  132. clrbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
  133. return 0;
  134. }
  135. static int bcm63xx_spi_set_speed(struct udevice *bus, uint speed)
  136. {
  137. struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  138. const unsigned long *regs = priv->regs;
  139. uint8_t clk_cfg;
  140. int i;
  141. /* default to lowest clock configuration */
  142. clk_cfg = SPI_CLK_0_391MHZ;
  143. /* find the closest clock configuration */
  144. for (i = 0; i < SPI_CLK_CNT; i++) {
  145. if (speed >= bcm63xx_spi_freq_table[i][0]) {
  146. clk_cfg = bcm63xx_spi_freq_table[i][1];
  147. break;
  148. }
  149. }
  150. /* write clock configuration */
  151. clrsetbits_8(priv->base + regs[SPI_CLK],
  152. SPI_CLK_SSOFF_MASK | SPI_CLK_MASK,
  153. clk_cfg | SPI_CLK_SSOFF_2);
  154. return 0;
  155. }
  156. /*
  157. * BCM63xx SPI driver doesn't allow keeping CS active between transfers since
  158. * they are HW controlled.
  159. * However, it provides a mechanism to prepend write transfers prior to read
  160. * transfers (with a maximum prepend of 15 bytes), which is usually enough for
  161. * SPI-connected flashes since reading requires prepending a write transfer of
  162. * 5 bytes.
  163. *
  164. * This implementation takes advantage of the prepend mechanism and combines
  165. * multiple transfers into a single one where possible (single/multiple write
  166. * transfer(s) followed by a final read/write transfer).
  167. * However, it's not possible to buffer reads, which means that read transfers
  168. * should always be done as the final ones.
  169. * On the other hand, take into account that combining write transfers into
  170. * a single one is just buffering and doesn't require prepend mechanism.
  171. */
  172. static int bcm63xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
  173. const void *dout, void *din, unsigned long flags)
  174. {
  175. struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
  176. const unsigned long *regs = priv->regs;
  177. size_t data_bytes = bitlen / 8;
  178. if (flags & SPI_XFER_BEGIN) {
  179. /* clear prepends */
  180. priv->tx_bytes = 0;
  181. /* initialize hardware */
  182. writeb_be(0, priv->base + regs[SPI_IR_MASK]);
  183. }
  184. if (din) {
  185. /* buffering reads not possible since cs is hw controlled */
  186. if (!(flags & SPI_XFER_END)) {
  187. printf("unable to buffer reads\n");
  188. return -EINVAL;
  189. }
  190. /* check rx size */
  191. if (data_bytes > regs[SPI_RX_SIZE]) {
  192. printf("max rx bytes exceeded\n");
  193. return -EMSGSIZE;
  194. }
  195. }
  196. if (dout) {
  197. /* check tx size */
  198. if (priv->tx_bytes + data_bytes > regs[SPI_TX_SIZE]) {
  199. printf("max tx bytes exceeded\n");
  200. return -EMSGSIZE;
  201. }
  202. /* copy tx data */
  203. memcpy_toio(priv->base + regs[SPI_TX] + priv->tx_bytes,
  204. dout, data_bytes);
  205. priv->tx_bytes += data_bytes;
  206. }
  207. if (flags & SPI_XFER_END) {
  208. struct dm_spi_slave_platdata *plat =
  209. dev_get_parent_platdata(dev);
  210. uint16_t val, cmd;
  211. int ret;
  212. /* determine control config */
  213. if (dout && !din) {
  214. /* buffered write transfers */
  215. val = priv->tx_bytes;
  216. val |= (SPI_CTL_TYPE_HD_W << regs[SPI_CTL_SHIFT]);
  217. priv->tx_bytes = 0;
  218. } else {
  219. if (dout && din && (flags & SPI_XFER_ONCE)) {
  220. /* full duplex read/write */
  221. val = data_bytes;
  222. val |= (SPI_CTL_TYPE_FD_RW <<
  223. regs[SPI_CTL_SHIFT]);
  224. priv->tx_bytes = 0;
  225. } else {
  226. /* prepended write transfer */
  227. val = data_bytes;
  228. val |= (SPI_CTL_TYPE_HD_R <<
  229. regs[SPI_CTL_SHIFT]);
  230. if (priv->tx_bytes > SPI_CMD_PREPEND_BYTES) {
  231. printf("max prepend bytes exceeded\n");
  232. return -EMSGSIZE;
  233. }
  234. }
  235. }
  236. if (regs[SPI_CTL_SHIFT] >= 8)
  237. writew_be(val, priv->base + regs[SPI_CTL]);
  238. else
  239. writeb_be(val, priv->base + regs[SPI_CTL]);
  240. /* clear interrupts */
  241. writeb_be(SPI_IR_CLEAR_MASK, priv->base + regs[SPI_IR_STAT]);
  242. /* issue the transfer */
  243. cmd = SPI_CMD_OP_START;
  244. cmd |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK;
  245. cmd |= (priv->tx_bytes << SPI_CMD_PREPEND_SHIFT);
  246. if (plat->mode & SPI_3WIRE)
  247. cmd |= SPI_CMD_3WIRE_MASK;
  248. writew_be(cmd, priv->base + regs[SPI_CMD]);
  249. /* enable interrupts */
  250. writeb_be(SPI_IR_DONE_MASK, priv->base + regs[SPI_IR_MASK]);
  251. ret = wait_for_bit_8(priv->base + regs[SPI_IR_STAT],
  252. SPI_IR_DONE_MASK, true, 1000, false);
  253. if (ret) {
  254. printf("interrupt timeout\n");
  255. return ret;
  256. }
  257. /* copy rx data */
  258. if (din)
  259. memcpy_fromio(din, priv->base + regs[SPI_RX],
  260. data_bytes);
  261. }
  262. return 0;
  263. }
  264. static const struct dm_spi_ops bcm63xx_spi_ops = {
  265. .cs_info = bcm63xx_spi_cs_info,
  266. .set_mode = bcm63xx_spi_set_mode,
  267. .set_speed = bcm63xx_spi_set_speed,
  268. .xfer = bcm63xx_spi_xfer,
  269. };
  270. static const unsigned long bcm6348_spi_regs[] = {
  271. [SPI_CLK] = SPI_6348_CLK,
  272. [SPI_CMD] = SPI_6348_CMD,
  273. [SPI_CTL] = SPI_6348_CTL,
  274. [SPI_CTL_SHIFT] = SPI_6348_CTL_SHIFT,
  275. [SPI_FILL] = SPI_6348_FILL,
  276. [SPI_IR_MASK] = SPI_6348_IR_MASK,
  277. [SPI_IR_STAT] = SPI_6348_IR_STAT,
  278. [SPI_RX] = SPI_6348_RX,
  279. [SPI_RX_SIZE] = SPI_6348_RX_SIZE,
  280. [SPI_TX] = SPI_6348_TX,
  281. [SPI_TX_SIZE] = SPI_6348_TX_SIZE,
  282. };
  283. static const unsigned long bcm6358_spi_regs[] = {
  284. [SPI_CLK] = SPI_6358_CLK,
  285. [SPI_CMD] = SPI_6358_CMD,
  286. [SPI_CTL] = SPI_6358_CTL,
  287. [SPI_CTL_SHIFT] = SPI_6358_CTL_SHIFT,
  288. [SPI_FILL] = SPI_6358_FILL,
  289. [SPI_IR_MASK] = SPI_6358_IR_MASK,
  290. [SPI_IR_STAT] = SPI_6358_IR_STAT,
  291. [SPI_RX] = SPI_6358_RX,
  292. [SPI_RX_SIZE] = SPI_6358_RX_SIZE,
  293. [SPI_TX] = SPI_6358_TX,
  294. [SPI_TX_SIZE] = SPI_6358_TX_SIZE,
  295. };
  296. static const struct udevice_id bcm63xx_spi_ids[] = {
  297. {
  298. .compatible = "brcm,bcm6348-spi",
  299. .data = (ulong)&bcm6348_spi_regs,
  300. }, {
  301. .compatible = "brcm,bcm6358-spi",
  302. .data = (ulong)&bcm6358_spi_regs,
  303. }, { /* sentinel */ }
  304. };
  305. static int bcm63xx_spi_child_pre_probe(struct udevice *dev)
  306. {
  307. struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
  308. const unsigned long *regs = priv->regs;
  309. struct spi_slave *slave = dev_get_parent_priv(dev);
  310. struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  311. /* check cs */
  312. if (plat->cs >= priv->num_cs) {
  313. printf("no cs %u\n", plat->cs);
  314. return -ENODEV;
  315. }
  316. /* max read/write sizes */
  317. slave->max_read_size = regs[SPI_RX_SIZE];
  318. slave->max_write_size = regs[SPI_TX_SIZE];
  319. return 0;
  320. }
  321. static int bcm63xx_spi_probe(struct udevice *dev)
  322. {
  323. struct bcm63xx_spi_priv *priv = dev_get_priv(dev);
  324. const unsigned long *regs =
  325. (const unsigned long *)dev_get_driver_data(dev);
  326. struct reset_ctl rst_ctl;
  327. struct clk clk;
  328. int ret;
  329. priv->base = dev_remap_addr(dev);
  330. if (!priv->base)
  331. return -EINVAL;
  332. priv->regs = regs;
  333. priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
  334. /* enable clock */
  335. ret = clk_get_by_index(dev, 0, &clk);
  336. if (ret < 0)
  337. return ret;
  338. ret = clk_enable(&clk);
  339. if (ret < 0)
  340. return ret;
  341. ret = clk_free(&clk);
  342. if (ret < 0)
  343. return ret;
  344. /* perform reset */
  345. ret = reset_get_by_index(dev, 0, &rst_ctl);
  346. if (ret < 0)
  347. return ret;
  348. ret = reset_deassert(&rst_ctl);
  349. if (ret < 0)
  350. return ret;
  351. ret = reset_free(&rst_ctl);
  352. if (ret < 0)
  353. return ret;
  354. /* initialize hardware */
  355. writeb_be(0, priv->base + regs[SPI_IR_MASK]);
  356. /* set fill register */
  357. writeb_be(0xff, priv->base + regs[SPI_FILL]);
  358. return 0;
  359. }
  360. U_BOOT_DRIVER(bcm63xx_spi) = {
  361. .name = "bcm63xx_spi",
  362. .id = UCLASS_SPI,
  363. .of_match = bcm63xx_spi_ids,
  364. .ops = &bcm63xx_spi_ops,
  365. .priv_auto_alloc_size = sizeof(struct bcm63xx_spi_priv),
  366. .child_pre_probe = bcm63xx_spi_child_pre_probe,
  367. .probe = bcm63xx_spi_probe,
  368. };