bcm63xx_hsspi.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
  6. * Copyright (C) 2000-2010 Broadcom Corporation
  7. * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <spi.h>
  13. #include <reset.h>
  14. #include <wait_bit.h>
  15. #include <asm/io.h>
  16. #define HSSPI_PP 0
  17. #define SPI_MAX_SYNC_CLOCK 30000000
  18. /* SPI Control register */
  19. #define SPI_CTL_REG 0x000
  20. #define SPI_CTL_CS_POL_SHIFT 0
  21. #define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT)
  22. #define SPI_CTL_CLK_GATE_SHIFT 16
  23. #define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT)
  24. #define SPI_CTL_CLK_POL_SHIFT 17
  25. #define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT)
  26. /* SPI Interrupts registers */
  27. #define SPI_IR_STAT_REG 0x008
  28. #define SPI_IR_ST_MASK_REG 0x00c
  29. #define SPI_IR_MASK_REG 0x010
  30. #define SPI_IR_CLEAR_ALL 0xff001f1f
  31. /* SPI Ping-Pong Command registers */
  32. #define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00)
  33. #define SPI_CMD_OP_SHIFT 0
  34. #define SPI_CMD_OP_START (0x1 << SPI_CMD_OP_SHIFT)
  35. #define SPI_CMD_PFL_SHIFT 8
  36. #define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT)
  37. #define SPI_CMD_SLAVE_SHIFT 12
  38. #define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT)
  39. /* SPI Ping-Pong Status registers */
  40. #define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04)
  41. #define SPI_STAT_SRCBUSY_SHIFT 1
  42. #define SPI_STAT_SRCBUSY_MASK (1 << SPI_STAT_SRCBUSY_SHIFT)
  43. /* SPI Profile Clock registers */
  44. #define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
  45. #define SPI_PFL_CLK_FREQ_SHIFT 0
  46. #define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
  47. #define SPI_PFL_CLK_RSTLOOP_SHIFT 15
  48. #define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
  49. /* SPI Profile Signal registers */
  50. #define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
  51. #define SPI_PFL_SIG_LATCHRIS_SHIFT 12
  52. #define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
  53. #define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13
  54. #define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT)
  55. #define SPI_PFL_SIG_ASYNCIN_SHIFT 16
  56. #define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)
  57. /* SPI Profile Mode registers */
  58. #define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08)
  59. #define SPI_PFL_MODE_FILL_SHIFT 0
  60. #define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
  61. #define SPI_PFL_MODE_MDRDSZ_SHIFT 16
  62. #define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
  63. #define SPI_PFL_MODE_MDWRSZ_SHIFT 18
  64. #define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
  65. #define SPI_PFL_MODE_3WIRE_SHIFT 20
  66. #define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT)
  67. /* SPI Ping-Pong FIFO registers */
  68. #define HSSPI_FIFO_SIZE 0x200
  69. #define HSSPI_FIFO_BASE (0x200 + \
  70. (HSSPI_FIFO_SIZE * HSSPI_PP))
  71. /* SPI Ping-Pong FIFO OP register */
  72. #define HSSPI_FIFO_OP_SIZE 0x2
  73. #define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00)
  74. #define HSSPI_FIFO_OP_BYTES_SHIFT 0
  75. #define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT)
  76. #define HSSPI_FIFO_OP_MBIT_SHIFT 11
  77. #define HSSPI_FIFO_OP_MBIT_MASK (1 << HSSPI_FIFO_OP_MBIT_SHIFT)
  78. #define HSSPI_FIFO_OP_CODE_SHIFT 13
  79. #define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT)
  80. #define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
  81. #define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
  82. struct bcm63xx_hsspi_priv {
  83. void __iomem *regs;
  84. ulong clk_rate;
  85. uint8_t num_cs;
  86. uint8_t cs_pols;
  87. uint speed;
  88. };
  89. static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
  90. struct spi_cs_info *info)
  91. {
  92. struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  93. if (cs >= priv->num_cs) {
  94. printf("no cs %u\n", cs);
  95. return -EINVAL;
  96. }
  97. return 0;
  98. }
  99. static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode)
  100. {
  101. struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  102. /* clock polarity */
  103. if (mode & SPI_CPOL)
  104. setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  105. else
  106. clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  107. return 0;
  108. }
  109. static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed)
  110. {
  111. struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  112. priv->speed = speed;
  113. return 0;
  114. }
  115. static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
  116. struct dm_spi_slave_platdata *plat)
  117. {
  118. uint32_t clr, set;
  119. /* profile clock */
  120. set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
  121. set = DIV_ROUND_UP(2048, set);
  122. set &= SPI_PFL_CLK_FREQ_MASK;
  123. set |= SPI_PFL_CLK_RSTLOOP_MASK;
  124. writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
  125. /* profile signal */
  126. set = 0;
  127. clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
  128. SPI_PFL_SIG_LATCHRIS_MASK |
  129. SPI_PFL_SIG_ASYNCIN_MASK;
  130. /* latch/launch config */
  131. if (plat->mode & SPI_CPHA)
  132. set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
  133. else
  134. set |= SPI_PFL_SIG_LATCHRIS_MASK;
  135. /* async clk */
  136. if (priv->speed > SPI_MAX_SYNC_CLOCK)
  137. set |= SPI_PFL_SIG_ASYNCIN_MASK;
  138. clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
  139. /* global control */
  140. set = 0;
  141. clr = 0;
  142. /* invert cs polarity */
  143. if (priv->cs_pols & BIT(plat->cs))
  144. clr |= BIT(plat->cs);
  145. else
  146. set |= BIT(plat->cs);
  147. /* invert dummy cs polarity */
  148. if (priv->cs_pols & BIT(!plat->cs))
  149. clr |= BIT(!plat->cs);
  150. else
  151. set |= BIT(!plat->cs);
  152. clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);
  153. }
  154. static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
  155. {
  156. /* restore cs polarities */
  157. clrsetbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
  158. priv->cs_pols);
  159. }
  160. /*
  161. * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
  162. * because they are controlled by HW.
  163. * However, it provides a mechanism to prepend write transfers prior to read
  164. * transfers (with a maximum prepend of 15 bytes), which is usually enough for
  165. * SPI-connected flashes since reading requires prepending a write transfer of
  166. * 5 bytes. On the other hand it also provides a way to invert each CS
  167. * polarity, not only between transfers like the older BCM63xx SPI driver, but
  168. * also the rest of the time.
  169. *
  170. * Instead of using the prepend mechanism, this implementation inverts the
  171. * polarity of both the desired CS and another dummy CS when the bus is
  172. * claimed. This way, the dummy CS is restored to its inactive value when
  173. * transfers are issued and the desired CS is preserved in its active value
  174. * all the time. This hack is also used in the upstream linux driver and
  175. * allows keeping CS active between trasnfers even if the HW doesn't give
  176. * this possibility.
  177. */
  178. static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
  179. const void *dout, void *din, unsigned long flags)
  180. {
  181. struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
  182. struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  183. size_t data_bytes = bitlen / 8;
  184. size_t step_size = HSSPI_FIFO_SIZE;
  185. uint16_t opcode = 0;
  186. uint32_t val;
  187. const uint8_t *tx = dout;
  188. uint8_t *rx = din;
  189. if (flags & SPI_XFER_BEGIN)
  190. bcm63xx_hsspi_activate_cs(priv, plat);
  191. /* fifo operation */
  192. if (tx && rx)
  193. opcode = HSSPI_FIFO_OP_READ_WRITE;
  194. else if (rx)
  195. opcode = HSSPI_FIFO_OP_CODE_R;
  196. else if (tx)
  197. opcode = HSSPI_FIFO_OP_CODE_W;
  198. if (opcode != HSSPI_FIFO_OP_CODE_R)
  199. step_size -= HSSPI_FIFO_OP_SIZE;
  200. /* dual mode */
  201. if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
  202. (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
  203. opcode |= HSSPI_FIFO_OP_MBIT_MASK;
  204. /* profile mode */
  205. val = SPI_PFL_MODE_FILL_MASK |
  206. SPI_PFL_MODE_MDRDSZ_MASK |
  207. SPI_PFL_MODE_MDWRSZ_MASK;
  208. if (plat->mode & SPI_3WIRE)
  209. val |= SPI_PFL_MODE_3WIRE_MASK;
  210. writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
  211. /* transfer loop */
  212. while (data_bytes > 0) {
  213. size_t curr_step = min(step_size, data_bytes);
  214. int ret;
  215. /* copy tx data */
  216. if (tx) {
  217. memcpy_toio(priv->regs + HSSPI_FIFO_BASE +
  218. HSSPI_FIFO_OP_SIZE, tx, curr_step);
  219. tx += curr_step;
  220. }
  221. /* set fifo operation */
  222. writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),
  223. priv->regs + HSSPI_FIFO_OP_REG);
  224. /* issue the transfer */
  225. val = SPI_CMD_OP_START;
  226. val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
  227. SPI_CMD_PFL_MASK;
  228. val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &
  229. SPI_CMD_SLAVE_MASK;
  230. writel(val, priv->regs + SPI_CMD_REG);
  231. /* wait for completion */
  232. ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
  233. SPI_STAT_SRCBUSY_MASK, false,
  234. 1000, false);
  235. if (ret) {
  236. printf("interrupt timeout\n");
  237. return ret;
  238. }
  239. /* copy rx data */
  240. if (rx) {
  241. memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,
  242. curr_step);
  243. rx += curr_step;
  244. }
  245. data_bytes -= curr_step;
  246. }
  247. if (flags & SPI_XFER_END)
  248. bcm63xx_hsspi_deactivate_cs(priv);
  249. return 0;
  250. }
  251. static const struct dm_spi_ops bcm63xx_hsspi_ops = {
  252. .cs_info = bcm63xx_hsspi_cs_info,
  253. .set_mode = bcm63xx_hsspi_set_mode,
  254. .set_speed = bcm63xx_hsspi_set_speed,
  255. .xfer = bcm63xx_hsspi_xfer,
  256. };
  257. static const struct udevice_id bcm63xx_hsspi_ids[] = {
  258. { .compatible = "brcm,bcm6328-hsspi", },
  259. { /* sentinel */ }
  260. };
  261. static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
  262. {
  263. struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
  264. struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  265. /* check cs */
  266. if (plat->cs >= priv->num_cs) {
  267. printf("no cs %u\n", plat->cs);
  268. return -ENODEV;
  269. }
  270. /* cs polarity */
  271. if (plat->mode & SPI_CS_HIGH)
  272. priv->cs_pols |= BIT(plat->cs);
  273. else
  274. priv->cs_pols &= ~BIT(plat->cs);
  275. return 0;
  276. }
  277. static int bcm63xx_hsspi_probe(struct udevice *dev)
  278. {
  279. struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev);
  280. struct reset_ctl rst_ctl;
  281. struct clk clk;
  282. int ret;
  283. priv->regs = dev_remap_addr(dev);
  284. if (!priv->regs)
  285. return -EINVAL;
  286. priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
  287. /* enable clock */
  288. ret = clk_get_by_name(dev, "hsspi", &clk);
  289. if (ret < 0)
  290. return ret;
  291. ret = clk_enable(&clk);
  292. if (ret < 0 && ret != -ENOSYS)
  293. return ret;
  294. ret = clk_free(&clk);
  295. if (ret < 0 && ret != -ENOSYS)
  296. return ret;
  297. /* get clock rate */
  298. ret = clk_get_by_name(dev, "pll", &clk);
  299. if (ret < 0 && ret != -ENOSYS)
  300. return ret;
  301. priv->clk_rate = clk_get_rate(&clk);
  302. ret = clk_free(&clk);
  303. if (ret < 0 && ret != -ENOSYS)
  304. return ret;
  305. /* perform reset */
  306. ret = reset_get_by_index(dev, 0, &rst_ctl);
  307. if (ret >= 0) {
  308. ret = reset_deassert(&rst_ctl);
  309. if (ret < 0)
  310. return ret;
  311. }
  312. ret = reset_free(&rst_ctl);
  313. if (ret < 0)
  314. return ret;
  315. /* initialize hardware */
  316. writel(0, priv->regs + SPI_IR_MASK_REG);
  317. /* clear pending interrupts */
  318. writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
  319. /* enable clk gate */
  320. setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
  321. /* read default cs polarities */
  322. priv->cs_pols = readl(priv->regs + SPI_CTL_REG) &
  323. SPI_CTL_CS_POL_MASK;
  324. return 0;
  325. }
  326. U_BOOT_DRIVER(bcm63xx_hsspi) = {
  327. .name = "bcm63xx_hsspi",
  328. .id = UCLASS_SPI,
  329. .of_match = bcm63xx_hsspi_ids,
  330. .ops = &bcm63xx_hsspi_ops,
  331. .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv),
  332. .child_pre_probe = bcm63xx_hsspi_child_pre_probe,
  333. .probe = bcm63xx_hsspi_probe,
  334. };