ath79_spi.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  4. */
  5. #include <common.h>
  6. #include <spi.h>
  7. #include <dm.h>
  8. #include <div64.h>
  9. #include <errno.h>
  10. #include <asm/io.h>
  11. #include <asm/addrspace.h>
  12. #include <asm/types.h>
  13. #include <dm/pinctrl.h>
  14. #include <mach/ar71xx_regs.h>
  15. /* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
  16. #define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1)
  17. #define ATH79_SPI_RRW_DELAY_FACTOR 12000
  18. #define ATH79_SPI_MHZ (1000 * 1000)
  19. struct ath79_spi_priv {
  20. void __iomem *regs;
  21. u32 rrw_delay;
  22. };
  23. static void spi_cs_activate(struct udevice *dev)
  24. {
  25. struct udevice *bus = dev_get_parent(dev);
  26. struct ath79_spi_priv *priv = dev_get_priv(bus);
  27. writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
  28. writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
  29. }
  30. static void spi_cs_deactivate(struct udevice *dev)
  31. {
  32. struct udevice *bus = dev_get_parent(dev);
  33. struct ath79_spi_priv *priv = dev_get_priv(bus);
  34. writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
  35. writel(0, priv->regs + AR71XX_SPI_REG_FS);
  36. }
  37. static int ath79_spi_claim_bus(struct udevice *dev)
  38. {
  39. return 0;
  40. }
  41. static int ath79_spi_release_bus(struct udevice *dev)
  42. {
  43. return 0;
  44. }
  45. static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
  46. const void *dout, void *din, unsigned long flags)
  47. {
  48. struct udevice *bus = dev_get_parent(dev);
  49. struct ath79_spi_priv *priv = dev_get_priv(bus);
  50. struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
  51. u8 *rx = din;
  52. const u8 *tx = dout;
  53. u8 curbyte, curbitlen, restbits;
  54. u32 bytes = bitlen / 8;
  55. u32 out, in;
  56. u64 tick;
  57. if (flags & SPI_XFER_BEGIN)
  58. spi_cs_activate(dev);
  59. restbits = (bitlen % 8);
  60. if (restbits)
  61. bytes++;
  62. out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
  63. while (bytes > 0) {
  64. bytes--;
  65. curbyte = 0;
  66. if (tx)
  67. curbyte = *tx++;
  68. if (restbits && !bytes) {
  69. curbitlen = restbits;
  70. curbyte <<= 8 - restbits;
  71. } else {
  72. curbitlen = 8;
  73. }
  74. for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
  75. if (curbyte & 0x80)
  76. out |= AR71XX_SPI_IOC_DO;
  77. else
  78. out &= ~(AR71XX_SPI_IOC_DO);
  79. writel(out, priv->regs + AR71XX_SPI_REG_IOC);
  80. /* delay for low level */
  81. if (priv->rrw_delay) {
  82. tick = get_ticks() + priv->rrw_delay;
  83. while (get_ticks() < tick)
  84. /*NOP*/;
  85. }
  86. writel(out | AR71XX_SPI_IOC_CLK,
  87. priv->regs + AR71XX_SPI_REG_IOC);
  88. /* delay for high level */
  89. if (priv->rrw_delay) {
  90. tick = get_ticks() + priv->rrw_delay;
  91. while (get_ticks() < tick)
  92. /*NOP*/;
  93. }
  94. curbyte <<= 1;
  95. }
  96. if (!bytes)
  97. writel(out, priv->regs + AR71XX_SPI_REG_IOC);
  98. in = readl(priv->regs + AR71XX_SPI_REG_RDS);
  99. if (rx) {
  100. if (restbits && !bytes)
  101. *rx++ = (in << (8 - restbits));
  102. else
  103. *rx++ = in;
  104. }
  105. }
  106. if (flags & SPI_XFER_END)
  107. spi_cs_deactivate(dev);
  108. return 0;
  109. }
  110. static int ath79_spi_set_speed(struct udevice *bus, uint speed)
  111. {
  112. struct ath79_spi_priv *priv = dev_get_priv(bus);
  113. u32 val, div = 0;
  114. u64 time;
  115. if (speed)
  116. div = get_bus_freq(0) / speed;
  117. if (div > 63)
  118. div = 63;
  119. if (div < 5)
  120. div = 5;
  121. /* calculate delay */
  122. time = get_tbclk();
  123. do_div(time, speed / 2);
  124. val = get_bus_freq(0) / ATH79_SPI_MHZ;
  125. val = ATH79_SPI_RRW_DELAY_FACTOR / val;
  126. if (time > val)
  127. priv->rrw_delay = time - val + 1;
  128. else
  129. priv->rrw_delay = 0;
  130. writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
  131. clrsetbits_be32(priv->regs + AR71XX_SPI_REG_CTRL,
  132. AR71XX_SPI_CTRL_DIV_MASK,
  133. ATH79_SPI_CLK_DIV(div));
  134. writel(0, priv->regs + AR71XX_SPI_REG_FS);
  135. return 0;
  136. }
  137. static int ath79_spi_set_mode(struct udevice *bus, uint mode)
  138. {
  139. return 0;
  140. }
  141. static int ath79_spi_probe(struct udevice *bus)
  142. {
  143. struct ath79_spi_priv *priv = dev_get_priv(bus);
  144. fdt_addr_t addr;
  145. addr = devfdt_get_addr(bus);
  146. if (addr == FDT_ADDR_T_NONE)
  147. return -EINVAL;
  148. priv->regs = map_physmem(addr,
  149. AR71XX_SPI_SIZE,
  150. MAP_NOCACHE);
  151. /* Init SPI Hardware, disable remap, set clock */
  152. writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
  153. writel(AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8),
  154. priv->regs + AR71XX_SPI_REG_CTRL);
  155. writel(0, priv->regs + AR71XX_SPI_REG_FS);
  156. return 0;
  157. }
  158. static int ath79_cs_info(struct udevice *bus, uint cs,
  159. struct spi_cs_info *info)
  160. {
  161. /* Always allow activity on CS 0/1/2 */
  162. if (cs >= 3)
  163. return -EINVAL;
  164. return 0;
  165. }
  166. static const struct dm_spi_ops ath79_spi_ops = {
  167. .claim_bus = ath79_spi_claim_bus,
  168. .release_bus = ath79_spi_release_bus,
  169. .xfer = ath79_spi_xfer,
  170. .set_speed = ath79_spi_set_speed,
  171. .set_mode = ath79_spi_set_mode,
  172. .cs_info = ath79_cs_info,
  173. };
  174. static const struct udevice_id ath79_spi_ids[] = {
  175. { .compatible = "qca,ar7100-spi" },
  176. {}
  177. };
  178. U_BOOT_DRIVER(ath79_spi) = {
  179. .name = "ath79_spi",
  180. .id = UCLASS_SPI,
  181. .of_match = ath79_spi_ids,
  182. .ops = &ath79_spi_ops,
  183. .priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
  184. .probe = ath79_spi_probe,
  185. };