dimm.h 2.9 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798
  1. #ifndef __dimm_h
  2. #define __dimm_h
  3. /*
  4. * Module name: %M%
  5. * Description:
  6. * Serial Presence Detect Definitions Module
  7. * SCCS identification: %I%
  8. * Branch: %B%
  9. * Sequence: %S%
  10. * Date newest applied delta was created (MM/DD/YY): %G%
  11. * Time newest applied delta was created (HH:MM:SS): %U%
  12. * SCCS file name %F%
  13. * Fully qualified SCCS file name:
  14. * %P%
  15. * Copyright:
  16. * (C) COPYRIGHT MOTOROLA, INC. 1996
  17. * ALL RIGHTS RESERVED
  18. * Notes:
  19. * 1. All data was taken from an IBM application note titled
  20. * "Serial Presence Detect Definitions".
  21. * History:
  22. * Date Who
  23. *
  24. * 10/24/96 Rob Baxter
  25. * Initial release.
  26. *
  27. */
  28. /*
  29. * serial PD byte assignment address map (256 byte EEPROM)
  30. */
  31. typedef struct dimm
  32. {
  33. uchar n_bytes; /* 00 number of bytes written/used */
  34. uchar t_bytes; /* 01 total number of bytes in serial PD device */
  35. uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */
  36. uchar n_row; /* 03 number of rows */
  37. uchar n_col; /* 04 number of columns */
  38. uchar n_banks; /* 05 number of banks */
  39. uchar data_w_lo; /* 06 data width */
  40. uchar data_w_hi; /* 07 data width */
  41. uchar ifl; /* 08 interface levels */
  42. uchar a_ras; /* 09 RAS access */
  43. uchar a_cas; /* 0A CAS access */
  44. uchar ct; /* 0B configuration type (non-parity/parity/ECC) */
  45. uchar refresh_rt; /* 0C refresh rate/type */
  46. uchar p_dram_o; /* 0D primary DRAM organization */
  47. uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */
  48. uchar reserved[17]; /* 0F reserved fields for future offerings */
  49. uchar ss_info[32]; /* 20 superset information (may be used in the future) */
  50. uchar m_info[64]; /* 40 manufacturer information (optional) */
  51. uchar unused[128]; /* 80 unused storage locations */
  52. } dimm_t;
  53. /*
  54. * memory type definitions
  55. */
  56. #define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */
  57. #define DIMM_MT_EDO 2 /* EDO (extended data out) */
  58. #define DIMM_MT_PN 3 /* pipelined nibble */
  59. #define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */
  60. /*
  61. * row addresses definitions
  62. */
  63. #define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */
  64. #define DIMM_RA_MASK 0x7f /* number of row addresses mask */
  65. /*
  66. * module interface levels definitions
  67. */
  68. #define DIMM_IFL_TTL 0 /* TTL/5V tolerant */
  69. #define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */
  70. #define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */
  71. #define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */
  72. #define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */
  73. /*
  74. * DIMM configuration type definitions
  75. */
  76. #define DIMM_CT_NONE 0 /* none */
  77. #define DIMM_CT_PARITY 1 /* parity */
  78. #define DIMM_CT_ECC 2 /* ECC */
  79. /*
  80. * row addresses definitions
  81. */
  82. #define DIMM_RRT_SR (1<<7) /* self refresh flag */
  83. #define DIMM_RRT_MASK 0x7f /* refresh rate mask */
  84. #define DIMM_RRT_NRML 0x00 /* normal (15.625us) */
  85. #define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */
  86. #define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */
  87. #define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */
  88. #define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */
  89. #define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */
  90. #endif /* __dimm_h */