test_burst_lib.S 3.3 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <config.h>
  8. #include <ppc_asm.tmpl>
  9. #include <ppc_defs.h>
  10. #include <asm/cache.h>
  11. #include <asm/mmu.h>
  12. #include "test_burst.h"
  13. .text
  14. /*
  15. * void mmu_init(void);
  16. *
  17. * This function turns the MMU on
  18. *
  19. * Three 8 MByte regions are mapped 1:1, uncached
  20. * - SDRAM lower 8 MByte
  21. * - SDRAM higher 8 MByte
  22. * - IMMR
  23. */
  24. .global mmu_init
  25. mmu_init:
  26. tlbia /* Invalidate all TLB entries */
  27. li r8, 0
  28. mtspr MI_CTR, r8 /* Set instruction control to zero */
  29. lis r8, MD_RESETVAL@h
  30. mtspr MD_CTR, r8 /* Set data TLB control */
  31. /* Now map the lower 8 Meg into the TLBs. For this quick hack,
  32. * we can load the instruction and data TLB registers with the
  33. * same values.
  34. */
  35. li r8, MI_EVALID /* Create EPN for address 0 */
  36. mtspr MI_EPN, r8
  37. mtspr MD_EPN, r8
  38. li r8, MI_PS8MEG /* Set 8M byte page */
  39. ori r8, r8, MI_SVALID /* Make it valid */
  40. mtspr MI_TWC, r8
  41. mtspr MD_TWC, r8
  42. li r8, MI_BOOTINIT|0x2 /* Create RPN for address 0 */
  43. mtspr MI_RPN, r8 /* Store TLB entry */
  44. mtspr MD_RPN, r8
  45. lis r8, MI_Kp@h /* Set the protection mode */
  46. mtspr MI_AP, r8
  47. mtspr MD_AP, r8
  48. /* Now map the higher 8 Meg into the TLBs. For this quick hack,
  49. * we can load the instruction and data TLB registers with the
  50. * same values.
  51. */
  52. lwz r9,20(r2) /* gd->ram_size */
  53. addis r9,r9,-0x80
  54. mr r8, r9 /* Higher 8 Meg in SDRAM */
  55. ori r8, r8, MI_EVALID /* Mark page valid */
  56. mtspr MI_EPN, r8
  57. mtspr MD_EPN, r8
  58. li r8, MI_PS8MEG /* Set 8M byte page */
  59. ori r8, r8, MI_SVALID /* Make it valid */
  60. mtspr MI_TWC, r8
  61. mtspr MD_TWC, r8
  62. mr r8, r9
  63. ori r8, r8, MI_BOOTINIT|0x2
  64. mtspr MI_RPN, r8 /* Store TLB entry */
  65. mtspr MD_RPN, r8
  66. lis r8, MI_Kp@h /* Set the protection mode */
  67. mtspr MI_AP, r8
  68. mtspr MD_AP, r8
  69. /* Map another 8 MByte at the IMMR to get the processor
  70. * internal registers (among other things).
  71. */
  72. mfspr r9, 638 /* Get current IMMR */
  73. andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
  74. mr r8, r9 /* Create vaddr for TLB */
  75. ori r8, r8, MD_EVALID /* Mark it valid */
  76. mtspr MD_EPN, r8
  77. li r8, MD_PS8MEG /* Set 8M byte page */
  78. ori r8, r8, MD_SVALID /* Make it valid */
  79. mtspr MD_TWC, r8
  80. mr r8, r9 /* Create paddr for TLB */
  81. ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
  82. mtspr MD_RPN, r8
  83. /* We now have the lower and higher 8 Meg mapped into TLB entries,
  84. * and the caches ready to work.
  85. */
  86. mfmsr r0
  87. ori r0,r0,MSR_DR|MSR_IR
  88. mtspr SRR1,r0
  89. mflr r0
  90. mtspr SRR0,r0
  91. SYNC
  92. rfi /* enables MMU */
  93. /*
  94. * void caches_init(void);
  95. */
  96. .globl caches_init
  97. caches_init:
  98. sync
  99. mfspr r3, IC_CST /* Clear error bits */
  100. mfspr r3, DC_CST
  101. lis r3, IDC_UNALL@h /* Unlock all */
  102. mtspr IC_CST, r3
  103. mtspr DC_CST, r3
  104. lis r3, IDC_INVALL@h /* Invalidate all */
  105. mtspr IC_CST, r3
  106. mtspr DC_CST, r3
  107. lis r3, IDC_ENABLE@h /* Enable all */
  108. mtspr IC_CST, r3
  109. mtspr DC_CST, r3
  110. blr
  111. /*
  112. * void flush_dcache_range(unsigned long start, unsigned long stop);
  113. */
  114. .global flush_dcache_range
  115. flush_dcache_range:
  116. li r5,CACHE_LINE_SIZE-1
  117. andc r3,r3,r5
  118. subf r4,r3,r4
  119. add r4,r4,r5
  120. srwi. r4,r4,LG_CACHE_LINE_SIZE
  121. beqlr
  122. mtctr r4
  123. 1: dcbf 0,r3
  124. addi r3,r3,CACHE_LINE_SIZE
  125. bdnz 1b
  126. sync /* wait for dcbf's to get to ram */
  127. blr
  128. /*
  129. * void disable_interrupts(void);
  130. */
  131. .global disable_interrupts
  132. disable_interrupts:
  133. mfmsr r0
  134. rlwinm r0,r0,0,17,15
  135. mtmsr r0
  136. blr