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  1. /*
  2. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  3. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  4. * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. /* U-Boot - Startup Code for PowerPC based Embedded Boards
  9. *
  10. *
  11. * The processor starts at 0x00000100 and the code is executed
  12. * from flash. The code is organized to be at an other address
  13. * in memory, but as long we don't jump around before relocating,
  14. * board_init lies at a quite high address and when the cpu has
  15. * jumped there, everything is ok.
  16. * This works because the cpu gives the FLASH (CS0) the whole
  17. * address space at startup, and board_init lies as a echo of
  18. * the flash somewhere up there in the memory map.
  19. *
  20. * board_init will change CS0 to be positioned at the correct
  21. * address and (s)dram will be positioned at address 0
  22. */
  23. #include <asm-offsets.h>
  24. #include <config.h>
  25. #include <mpc8xx.h>
  26. #include <version.h>
  27. #include <ppc_asm.tmpl>
  28. #include <ppc_defs.h>
  29. #include <asm/cache.h>
  30. #include <asm/mmu.h>
  31. #include <asm/u-boot.h>
  32. /* We don't want the MMU yet.
  33. */
  34. #undef MSR_KERNEL
  35. #define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
  36. /*
  37. * Set up GOT: Global Offset Table
  38. *
  39. * Use r12 to access the GOT
  40. */
  41. START_GOT
  42. GOT_ENTRY(_GOT2_TABLE_)
  43. GOT_ENTRY(_FIXUP_TABLE_)
  44. GOT_ENTRY(_start)
  45. GOT_ENTRY(_start_of_vectors)
  46. GOT_ENTRY(_end_of_vectors)
  47. GOT_ENTRY(transfer_to_handler)
  48. GOT_ENTRY(__init_end)
  49. GOT_ENTRY(__bss_end)
  50. GOT_ENTRY(__bss_start)
  51. END_GOT
  52. /*
  53. * r3 - 1st arg to board_init(): IMMP pointer
  54. * r4 - 2nd arg to board_init(): boot flag
  55. */
  56. .text
  57. .long 0x27051956 /* U-Boot Magic Number */
  58. .globl version_string
  59. version_string:
  60. .ascii U_BOOT_VERSION_STRING, "\0"
  61. . = EXC_OFF_SYS_RESET
  62. .globl _start
  63. _start:
  64. lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
  65. mtspr 638, r3
  66. /* Initialize machine status; enable machine check interrupt */
  67. /*----------------------------------------------------------------------*/
  68. li r3, MSR_KERNEL /* Set ME, RI flags */
  69. mtmsr r3
  70. mtspr SRR1, r3 /* Make SRR1 match MSR */
  71. mfspr r3, ICR /* clear Interrupt Cause Register */
  72. /* Initialize debug port registers */
  73. /*----------------------------------------------------------------------*/
  74. xor r0, r0, r0 /* Clear R0 */
  75. mtspr LCTRL1, r0 /* Initialize debug port regs */
  76. mtspr LCTRL2, r0
  77. mtspr COUNTA, r0
  78. mtspr COUNTB, r0
  79. /* Reset the caches */
  80. /*----------------------------------------------------------------------*/
  81. mfspr r3, IC_CST /* Clear error bits */
  82. mfspr r3, DC_CST
  83. lis r3, IDC_UNALL@h /* Unlock all */
  84. mtspr IC_CST, r3
  85. mtspr DC_CST, r3
  86. lis r3, IDC_INVALL@h /* Invalidate all */
  87. mtspr IC_CST, r3
  88. mtspr DC_CST, r3
  89. lis r3, IDC_DISABLE@h /* Disable data cache */
  90. mtspr DC_CST, r3
  91. #if !defined(CONFIG_SYS_DELAYED_ICACHE)
  92. /* On IP860 and PCU E,
  93. * we cannot enable IC yet
  94. */
  95. lis r3, IDC_ENABLE@h /* Enable instruction cache */
  96. #endif
  97. mtspr IC_CST, r3
  98. /* invalidate all tlb's */
  99. /*----------------------------------------------------------------------*/
  100. tlbia
  101. isync
  102. /*
  103. * Calculate absolute address in FLASH and jump there
  104. *----------------------------------------------------------------------*/
  105. lis r3, CONFIG_SYS_MONITOR_BASE@h
  106. ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
  107. addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
  108. mtlr r3
  109. blr
  110. in_flash:
  111. /* initialize some SPRs that are hard to access from C */
  112. /*----------------------------------------------------------------------*/
  113. lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */
  114. ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
  115. /* Note: R0 is still 0 here */
  116. stwu r0, -4(r1) /* clear final stack frame so that */
  117. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  118. /*
  119. * Disable serialized ifetch and show cycles
  120. * (i.e. set processor to normal mode).
  121. * This is also a silicon bug workaround, see errata
  122. */
  123. li r2, 0x0007
  124. mtspr ICTRL, r2
  125. /* Set up debug mode entry */
  126. lis r2, CONFIG_SYS_DER@h
  127. ori r2, r2, CONFIG_SYS_DER@l
  128. mtspr DER, r2
  129. /* let the C-code set up the rest */
  130. /* */
  131. /* Be careful to keep code relocatable ! */
  132. /*----------------------------------------------------------------------*/
  133. GET_GOT /* initialize GOT access */
  134. /* r3: IMMR */
  135. bl cpu_init_f /* run low-level CPU init code (from Flash) */
  136. bl board_init_f /* run 1st part of board init code (from Flash) */
  137. /* NOTREACHED - board_init_f() does not return */
  138. .globl _start_of_vectors
  139. _start_of_vectors:
  140. /* Machine check */
  141. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  142. /* Data Storage exception. "Never" generated on the 860. */
  143. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  144. /* Instruction Storage exception. "Never" generated on the 860. */
  145. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  146. /* External Interrupt exception. */
  147. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  148. /* Alignment exception. */
  149. . = 0x600
  150. Alignment:
  151. EXCEPTION_PROLOG(SRR0, SRR1)
  152. mfspr r4,DAR
  153. stw r4,_DAR(r21)
  154. mfspr r5,DSISR
  155. stw r5,_DSISR(r21)
  156. addi r3,r1,STACK_FRAME_OVERHEAD
  157. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  158. /* Program check exception */
  159. . = 0x700
  160. ProgramCheck:
  161. EXCEPTION_PROLOG(SRR0, SRR1)
  162. addi r3,r1,STACK_FRAME_OVERHEAD
  163. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  164. MSR_KERNEL, COPY_EE)
  165. /* No FPU on MPC8xx. This exception is not supposed to happen.
  166. */
  167. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  168. /* I guess we could implement decrementer, and may have
  169. * to someday for timekeeping.
  170. */
  171. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  172. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  173. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  174. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  175. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  176. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  177. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  178. /* On the MPC8xx, this is a software emulation interrupt. It occurs
  179. * for all unimplemented and illegal instructions.
  180. */
  181. STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
  182. STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
  183. STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
  184. STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
  185. STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
  186. STD_EXCEPTION(0x1500, Reserved5, UnknownException)
  187. STD_EXCEPTION(0x1600, Reserved6, UnknownException)
  188. STD_EXCEPTION(0x1700, Reserved7, UnknownException)
  189. STD_EXCEPTION(0x1800, Reserved8, UnknownException)
  190. STD_EXCEPTION(0x1900, Reserved9, UnknownException)
  191. STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
  192. STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
  193. STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
  194. STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
  195. STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
  196. STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
  197. .globl _end_of_vectors
  198. _end_of_vectors:
  199. . = 0x2000
  200. /*
  201. * This code finishes saving the registers to the exception frame
  202. * and jumps to the appropriate handler for the exception.
  203. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  204. */
  205. .globl transfer_to_handler
  206. transfer_to_handler:
  207. stw r22,_NIP(r21)
  208. lis r22,MSR_POW@h
  209. andc r23,r23,r22
  210. stw r23,_MSR(r21)
  211. SAVE_GPR(7, r21)
  212. SAVE_4GPRS(8, r21)
  213. SAVE_8GPRS(12, r21)
  214. SAVE_8GPRS(24, r21)
  215. mflr r23
  216. andi. r24,r23,0x3f00 /* get vector offset */
  217. stw r24,TRAP(r21)
  218. li r22,0
  219. stw r22,RESULT(r21)
  220. mtspr SPRG2,r22 /* r1 is now kernel sp */
  221. lwz r24,0(r23) /* virtual address of handler */
  222. lwz r23,4(r23) /* where to go when done */
  223. mtspr SRR0,r24
  224. mtspr SRR1,r20
  225. mtlr r23
  226. SYNC
  227. rfi /* jump to handler, enable MMU */
  228. int_return:
  229. mfmsr r28 /* Disable interrupts */
  230. li r4,0
  231. ori r4,r4,MSR_EE
  232. andc r28,r28,r4
  233. SYNC /* Some chip revs need this... */
  234. mtmsr r28
  235. SYNC
  236. lwz r2,_CTR(r1)
  237. lwz r0,_LINK(r1)
  238. mtctr r2
  239. mtlr r0
  240. lwz r2,_XER(r1)
  241. lwz r0,_CCR(r1)
  242. mtspr XER,r2
  243. mtcrf 0xFF,r0
  244. REST_10GPRS(3, r1)
  245. REST_10GPRS(13, r1)
  246. REST_8GPRS(23, r1)
  247. REST_GPR(31, r1)
  248. lwz r2,_NIP(r1) /* Restore environment */
  249. lwz r0,_MSR(r1)
  250. mtspr SRR0,r2
  251. mtspr SRR1,r0
  252. lwz r0,GPR0(r1)
  253. lwz r2,GPR2(r1)
  254. lwz r1,GPR1(r1)
  255. SYNC
  256. rfi
  257. /* Cache functions.
  258. */
  259. .globl icache_enable
  260. icache_enable:
  261. SYNC
  262. lis r3, IDC_INVALL@h
  263. mtspr IC_CST, r3
  264. lis r3, IDC_ENABLE@h
  265. mtspr IC_CST, r3
  266. blr
  267. .globl icache_disable
  268. icache_disable:
  269. SYNC
  270. lis r3, IDC_DISABLE@h
  271. mtspr IC_CST, r3
  272. blr
  273. .globl icache_status
  274. icache_status:
  275. mfspr r3, IC_CST
  276. srwi r3, r3, 31 /* >>31 => select bit 0 */
  277. blr
  278. .globl dcache_enable
  279. dcache_enable:
  280. #if 0
  281. SYNC
  282. #endif
  283. #if 1
  284. lis r3, 0x0400 /* Set cache mode with MMU off */
  285. mtspr MD_CTR, r3
  286. #endif
  287. lis r3, IDC_INVALL@h
  288. mtspr DC_CST, r3
  289. #if 0
  290. lis r3, DC_SFWT@h
  291. mtspr DC_CST, r3
  292. #endif
  293. lis r3, IDC_ENABLE@h
  294. mtspr DC_CST, r3
  295. blr
  296. .globl dcache_disable
  297. dcache_disable:
  298. SYNC
  299. lis r3, IDC_DISABLE@h
  300. mtspr DC_CST, r3
  301. lis r3, IDC_INVALL@h
  302. mtspr DC_CST, r3
  303. blr
  304. .globl dcache_status
  305. dcache_status:
  306. mfspr r3, DC_CST
  307. srwi r3, r3, 31 /* >>31 => select bit 0 */
  308. blr
  309. .globl dc_read
  310. dc_read:
  311. mtspr DC_ADR, r3
  312. mfspr r3, DC_DAT
  313. blr
  314. /*
  315. * unsigned int get_immr (unsigned int mask)
  316. *
  317. * return (mask ? (IMMR & mask) : IMMR);
  318. */
  319. .globl get_immr
  320. get_immr:
  321. mr r4,r3 /* save mask */
  322. mfspr r3, IMMR /* IMMR */
  323. cmpwi 0,r4,0 /* mask != 0 ? */
  324. beq 4f
  325. and r3,r3,r4 /* IMMR & mask */
  326. 4:
  327. blr
  328. .globl get_pvr
  329. get_pvr:
  330. mfspr r3, PVR
  331. blr
  332. .globl wr_ic_cst
  333. wr_ic_cst:
  334. mtspr IC_CST, r3
  335. blr
  336. .globl rd_ic_cst
  337. rd_ic_cst:
  338. mfspr r3, IC_CST
  339. blr
  340. .globl wr_ic_adr
  341. wr_ic_adr:
  342. mtspr IC_ADR, r3
  343. blr
  344. .globl wr_dc_cst
  345. wr_dc_cst:
  346. mtspr DC_CST, r3
  347. blr
  348. .globl rd_dc_cst
  349. rd_dc_cst:
  350. mfspr r3, DC_CST
  351. blr
  352. .globl wr_dc_adr
  353. wr_dc_adr:
  354. mtspr DC_ADR, r3
  355. blr
  356. /*------------------------------------------------------------------------------*/
  357. /*
  358. * void relocate_code (addr_sp, gd, addr_moni)
  359. *
  360. * This "function" does not return, instead it continues in RAM
  361. * after relocating the monitor code.
  362. *
  363. * r3 = dest
  364. * r4 = src
  365. * r5 = length in bytes
  366. * r6 = cachelinesize
  367. */
  368. .globl relocate_code
  369. relocate_code:
  370. mr r1, r3 /* Set new stack pointer */
  371. mr r9, r4 /* Save copy of Global Data pointer */
  372. mr r10, r5 /* Save copy of Destination Address */
  373. GET_GOT
  374. mr r3, r5 /* Destination Address */
  375. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  376. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  377. lwz r5, GOT(__init_end)
  378. sub r5, r5, r4
  379. li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  380. /*
  381. * Fix GOT pointer:
  382. *
  383. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  384. *
  385. * Offset:
  386. */
  387. sub r15, r10, r4
  388. /* First our own GOT */
  389. add r12, r12, r15
  390. /* then the one used by the C code */
  391. add r30, r30, r15
  392. /*
  393. * Now relocate code
  394. */
  395. cmplw cr1,r3,r4
  396. addi r0,r5,3
  397. srwi. r0,r0,2
  398. beq cr1,4f /* In place copy is not necessary */
  399. beq 7f /* Protect against 0 count */
  400. mtctr r0
  401. bge cr1,2f
  402. la r8,-4(r4)
  403. la r7,-4(r3)
  404. 1: lwzu r0,4(r8)
  405. stwu r0,4(r7)
  406. bdnz 1b
  407. b 4f
  408. 2: slwi r0,r0,2
  409. add r8,r4,r0
  410. add r7,r3,r0
  411. 3: lwzu r0,-4(r8)
  412. stwu r0,-4(r7)
  413. bdnz 3b
  414. /*
  415. * Now flush the cache: note that we must start from a cache aligned
  416. * address. Otherwise we might miss one cache line.
  417. */
  418. 4: cmpwi r6,0
  419. add r5,r3,r5
  420. beq 7f /* Always flush prefetch queue in any case */
  421. subi r0,r6,1
  422. andc r3,r3,r0
  423. mr r4,r3
  424. 5: dcbst 0,r4
  425. add r4,r4,r6
  426. cmplw r4,r5
  427. blt 5b
  428. sync /* Wait for all dcbst to complete on bus */
  429. mr r4,r3
  430. 6: icbi 0,r4
  431. add r4,r4,r6
  432. cmplw r4,r5
  433. blt 6b
  434. 7: sync /* Wait for all icbi to complete on bus */
  435. isync
  436. /*
  437. * We are done. Do not return, instead branch to second part of board
  438. * initialization, now running from RAM.
  439. */
  440. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  441. mtlr r0
  442. blr
  443. in_ram:
  444. /*
  445. * Relocation Function, r12 point to got2+0x8000
  446. *
  447. * Adjust got2 pointers, no need to check for 0, this code
  448. * already puts a few entries in the table.
  449. */
  450. li r0,__got2_entries@sectoff@l
  451. la r3,GOT(_GOT2_TABLE_)
  452. lwz r11,GOT(_GOT2_TABLE_)
  453. mtctr r0
  454. sub r11,r3,r11
  455. addi r3,r3,-4
  456. 1: lwzu r0,4(r3)
  457. cmpwi r0,0
  458. beq- 2f
  459. add r0,r0,r11
  460. stw r0,0(r3)
  461. 2: bdnz 1b
  462. /*
  463. * Now adjust the fixups and the pointers to the fixups
  464. * in case we need to move ourselves again.
  465. */
  466. li r0,__fixup_entries@sectoff@l
  467. lwz r3,GOT(_FIXUP_TABLE_)
  468. cmpwi r0,0
  469. mtctr r0
  470. addi r3,r3,-4
  471. beq 4f
  472. 3: lwzu r4,4(r3)
  473. lwzux r0,r4,r11
  474. cmpwi r0,0
  475. add r0,r0,r11
  476. stw r4,0(r3)
  477. beq- 5f
  478. stw r0,0(r4)
  479. 5: bdnz 3b
  480. 4:
  481. clear_bss:
  482. /*
  483. * Now clear BSS segment
  484. */
  485. lwz r3,GOT(__bss_start)
  486. lwz r4,GOT(__bss_end)
  487. cmplw 0, r3, r4
  488. beq 6f
  489. li r0, 0
  490. 5:
  491. stw r0, 0(r3)
  492. addi r3, r3, 4
  493. cmplw 0, r3, r4
  494. bne 5b
  495. 6:
  496. mr r3, r9 /* Global Data pointer */
  497. mr r4, r10 /* Destination Address */
  498. bl board_init_r
  499. /*
  500. * Copy exception vector code to low memory
  501. *
  502. * r3: dest_addr
  503. * r7: source address, r8: end address, r9: target address
  504. */
  505. .globl trap_init
  506. trap_init:
  507. mflr r4 /* save link register */
  508. GET_GOT
  509. lwz r7, GOT(_start)
  510. lwz r8, GOT(_end_of_vectors)
  511. li r9, 0x100 /* reset vector always at 0x100 */
  512. cmplw 0, r7, r8
  513. bgelr /* return if r7>=r8 - just in case */
  514. 1:
  515. lwz r0, 0(r7)
  516. stw r0, 0(r9)
  517. addi r7, r7, 4
  518. addi r9, r9, 4
  519. cmplw 0, r7, r8
  520. bne 1b
  521. /*
  522. * relocate `hdlr' and `int_return' entries
  523. */
  524. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  525. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  526. 2:
  527. bl trap_reloc
  528. addi r7, r7, 0x100 /* next exception vector */
  529. cmplw 0, r7, r8
  530. blt 2b
  531. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  532. bl trap_reloc
  533. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  534. bl trap_reloc
  535. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  536. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  537. 3:
  538. bl trap_reloc
  539. addi r7, r7, 0x100 /* next exception vector */
  540. cmplw 0, r7, r8
  541. blt 3b
  542. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  543. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  544. 4:
  545. bl trap_reloc
  546. addi r7, r7, 0x100 /* next exception vector */
  547. cmplw 0, r7, r8
  548. blt 4b
  549. mtlr r4 /* restore link register */
  550. blr