speed.c 11 KB

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  1. /*
  2. * (C) Copyright 2000-2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <mpc8xx.h>
  9. #include <asm/processor.h>
  10. DECLARE_GLOBAL_DATA_PTR;
  11. #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CONFIG_SYS_MEASURE_CPUCLK) || defined(DEBUG)
  12. #define PITC_SHIFT 16
  13. #define PITR_SHIFT 16
  14. /* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
  15. #define SPEED_PIT_COUNTS 58
  16. #define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT)
  17. #define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT)
  18. /* Access functions for the Machine State Register */
  19. static __inline__ unsigned long get_msr(void)
  20. {
  21. unsigned long msr;
  22. asm volatile("mfmsr %0" : "=r" (msr) :);
  23. return msr;
  24. }
  25. static __inline__ void set_msr(unsigned long msr)
  26. {
  27. asm volatile("mtmsr %0" : : "r" (msr));
  28. }
  29. /* ------------------------------------------------------------------------- */
  30. /*
  31. * Measure CPU clock speed (core clock GCLK1, GCLK2),
  32. * also determine bus clock speed (checking bus divider factor)
  33. *
  34. * (Approx. GCLK frequency in Hz)
  35. *
  36. * Initializes timer 2 and PIT, but disables them before return.
  37. * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4]
  38. *
  39. * When measuring the CPU clock against the PIT, we count cpu clocks
  40. * for 58/8192 seconds with a prescale divide by 177 for the cpu clock.
  41. * These strange values for the timing interval and prescaling are used
  42. * because the formula for the CPU clock is:
  43. *
  44. * CPU clock = count * (177 * (8192 / 58))
  45. *
  46. * = count * 24999.7241
  47. *
  48. * which is very close to
  49. *
  50. * = count * 25000
  51. *
  52. * Since the count gives the CPU clock divided by 25000, we can get
  53. * the CPU clock rounded to the nearest 0.1 MHz by
  54. *
  55. * CPU clock = ((count + 2) / 4) * 100000;
  56. *
  57. * The rounding is important since the measurement is sometimes going
  58. * to be high or low by 0.025 MHz, depending on exactly how the clocks
  59. * and counters interact. By rounding we get the exact answer for any
  60. * CPU clock that is an even multiple of 0.1 MHz.
  61. */
  62. unsigned long measure_gclk(void)
  63. {
  64. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  65. volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
  66. ulong timer2_val;
  67. ulong msr_val;
  68. #ifdef CONFIG_SYS_8XX_XIN
  69. /* dont use OSCM, only use EXTCLK/512 */
  70. immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
  71. #else
  72. immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
  73. #endif
  74. /* Reset + Stop Timer 2, no cascading
  75. */
  76. timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2);
  77. /* Keep stopped, halt in debug mode
  78. */
  79. timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2);
  80. /* Timer 2 setup:
  81. * Output ref. interrupt disable, int. clock
  82. * Prescale by 177. Note that prescaler divides by value + 1
  83. * so we must subtract 1 here.
  84. */
  85. timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;
  86. timerp->cpmt_tcn2 = 0; /* reset state */
  87. timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */
  88. /*
  89. * PIT setup:
  90. *
  91. * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
  92. * so the count value would be SPEED_PITC_COUNTS - 1.
  93. * But there would be an uncertainty in the start time of 1/4
  94. * count since when we enable the PIT the count is not
  95. * synchronized to the 32768 Hz oscillator. The trick here is
  96. * to start the count higher and wait until the PIT count
  97. * changes to the required value before starting timer 2.
  98. *
  99. * One count high should be enough, but occasionally the start
  100. * is off by 1 or 2 counts of 32768 Hz. With the start value
  101. * set two counts high it seems very reliable.
  102. */
  103. immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */
  104. immr->im_sit.sit_pitc = SPEED_PITC_INIT;
  105. immr->im_sitk.sitk_piscrk = KAPWR_KEY;
  106. immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
  107. /*
  108. * Start measurement - disable interrupts, just in case
  109. */
  110. msr_val = get_msr ();
  111. set_msr (msr_val & ~MSR_EE);
  112. immr->im_sit.sit_piscr |= PISCR_PTE;
  113. /* spin until get exact count when we want to start */
  114. while (immr->im_sit.sit_pitr > SPEED_PITC);
  115. timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */
  116. while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
  117. timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */
  118. /* re-enable external interrupts if they were on */
  119. set_msr (msr_val);
  120. /* Disable timer and PIT
  121. */
  122. timer2_val = timerp->cpmt_tcn2; /* save before reset timer */
  123. timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
  124. immr->im_sit.sit_piscr &= ~PISCR_PTE;
  125. #if defined(CONFIG_SYS_8XX_XIN)
  126. /* not using OSCM, using XIN, so scale appropriately */
  127. return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L;
  128. #else
  129. return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
  130. #endif
  131. }
  132. #endif
  133. void get_brgclk(uint sccr)
  134. {
  135. uint divider = 0;
  136. switch((sccr&SCCR_DFBRG11)>>11){
  137. case 0:
  138. divider = 1;
  139. break;
  140. case 1:
  141. divider = 4;
  142. break;
  143. case 2:
  144. divider = 16;
  145. break;
  146. case 3:
  147. divider = 64;
  148. break;
  149. }
  150. gd->arch.brg_clk = gd->cpu_clk/divider;
  151. }
  152. #if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
  153. /*
  154. * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
  155. * or (if it is not defined) measure_gclk() (which uses the ref clock)
  156. * from above.
  157. */
  158. int get_clocks (void)
  159. {
  160. uint immr = get_immr (0); /* Return full IMMR contents */
  161. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  162. uint sccr = immap->im_clkrst.car_sccr;
  163. /*
  164. * If for some reason measuring the gclk frequency won't
  165. * work, we return the hardwired value.
  166. * (For example, the cogent CMA286-60 CPU module has no
  167. * separate oscillator for PITRTCLK)
  168. */
  169. #if defined(CONFIG_8xx_GCLK_FREQ)
  170. gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
  171. #elif defined(CONFIG_8xx_OSCLK)
  172. #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
  173. uint pll = immap->im_clkrst.car_plprcr;
  174. uint clk;
  175. if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
  176. clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) *
  177. (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) /
  178. (1<<PLPRCR_val(S));
  179. } else {
  180. clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1);
  181. }
  182. if (pll & PLPRCR_CSRC) { /* Low frequency division factor is used */
  183. gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7));
  184. } else { /* High frequency division factor is used */
  185. gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7));
  186. }
  187. #else
  188. gd->cpu_clk = measure_gclk();
  189. #endif /* CONFIG_8xx_GCLK_FREQ */
  190. if ((sccr & SCCR_EBDF11) == 0) {
  191. /* No Bus Divider active */
  192. gd->bus_clk = gd->cpu_clk;
  193. } else {
  194. /* The MPC8xx has only one BDF: half clock speed */
  195. gd->bus_clk = gd->cpu_clk / 2;
  196. }
  197. get_brgclk(sccr);
  198. return (0);
  199. }
  200. #else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */
  201. static long init_pll_866 (long clk);
  202. /* Adjust sdram refresh rate to actual CPU clock.
  203. */
  204. static int sdram_adjust_866(void)
  205. {
  206. volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  207. long mamr;
  208. mamr = immr->im_memctl.memc_mamr;
  209. mamr &= ~MAMR_PTA_MSK;
  210. mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
  211. immr->im_memctl.memc_mamr = mamr;
  212. return 0;
  213. }
  214. /*
  215. * Adjust sdram refresh rate to actual CPU clock
  216. * and set timebase source according to actual CPU clock
  217. */
  218. static int adjust_sdram_tbs_8xx(void)
  219. {
  220. #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) && \
  221. !defined(CONFIG_TQM885D)
  222. volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  223. long mamr;
  224. long sccr;
  225. mamr = immr->im_memctl.memc_mamr;
  226. mamr &= ~MAMR_PTA_MSK;
  227. mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
  228. immr->im_memctl.memc_mamr = mamr;
  229. if (gd->cpu_clk < 67000000) {
  230. sccr = immr->im_clkrst.car_sccr;
  231. sccr |= SCCR_TBS;
  232. immr->im_clkrst.car_sccr = sccr;
  233. }
  234. #endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
  235. return 0;
  236. }
  237. /* This function sets up PLL (init_pll_866() is called) and
  238. * fills gd->cpu_clk and gd->bus_clk according to the environment
  239. * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
  240. * contains invalid value).
  241. * This functions requires an MPC866 or newer series CPU.
  242. */
  243. int get_clocks(void)
  244. {
  245. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  246. char tmp[64];
  247. long cpuclk = 0;
  248. long sccr_reg;
  249. int ret;
  250. if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0)
  251. cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
  252. if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk))
  253. cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
  254. gd->cpu_clk = init_pll_866 (cpuclk);
  255. #if defined(CONFIG_SYS_MEASURE_CPUCLK)
  256. gd->cpu_clk = measure_gclk ();
  257. #endif
  258. get_brgclk(immr->im_clkrst.car_sccr);
  259. /* if cpu clock <= 66 MHz then set bus division factor to 1,
  260. * otherwise set it to 2
  261. */
  262. sccr_reg = immr->im_clkrst.car_sccr;
  263. sccr_reg &= ~SCCR_EBDF11;
  264. if (gd->cpu_clk <= 66000000) {
  265. sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
  266. gd->bus_clk = gd->cpu_clk;
  267. } else {
  268. sccr_reg |= SCCR_EBDF01; /* bus division factor = 2 */
  269. gd->bus_clk = gd->cpu_clk / 2;
  270. }
  271. immr->im_clkrst.car_sccr = sccr_reg;
  272. ret = sdram_adjust_866();
  273. if (ret)
  274. return ret;
  275. return adjust_sdram_tbs_8xx();
  276. }
  277. /* Configure PLL for MPC866/859/885 CPU series
  278. * PLL multiplication factor is set to the value nearest to the desired clk,
  279. * assuming a oscclk of 10 MHz.
  280. */
  281. static long init_pll_866 (long clk)
  282. {
  283. extern void plprcr_write_866 (long);
  284. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  285. long n, plprcr;
  286. char mfi, mfn, mfd, s, pdf;
  287. long step_mfi, step_mfn;
  288. if (clk < 20000000) {
  289. clk *= 2;
  290. pdf = 1;
  291. } else {
  292. pdf = 0;
  293. }
  294. if (clk < 40000000) {
  295. s = 2;
  296. step_mfi = CONFIG_8xx_OSCLK / 4;
  297. mfd = 7;
  298. step_mfn = CONFIG_8xx_OSCLK / 30;
  299. } else if (clk < 80000000) {
  300. s = 1;
  301. step_mfi = CONFIG_8xx_OSCLK / 2;
  302. mfd = 14;
  303. step_mfn = CONFIG_8xx_OSCLK / 30;
  304. } else {
  305. s = 0;
  306. step_mfi = CONFIG_8xx_OSCLK;
  307. mfd = 29;
  308. step_mfn = CONFIG_8xx_OSCLK / 30;
  309. }
  310. /* Calculate integer part of multiplication factor
  311. */
  312. n = clk / step_mfi;
  313. mfi = (char)n;
  314. /* Calculate numerator of fractional part of multiplication factor
  315. */
  316. n = clk - (n * step_mfi);
  317. mfn = (char)(n / step_mfn);
  318. /* Calculate effective clk
  319. */
  320. n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1);
  321. immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
  322. plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
  323. | PLPRCR_MFD_MSK | PLPRCR_S_MSK
  324. | PLPRCR_MFI_MSK | PLPRCR_DBRMO
  325. | PLPRCR_PDF_MSK))
  326. | (mfn << PLPRCR_MFN_SHIFT)
  327. | (mfd << PLPRCR_MFD_SHIFT)
  328. | (s << PLPRCR_S_SHIFT)
  329. | (mfi << PLPRCR_MFI_SHIFT)
  330. | (pdf << PLPRCR_PDF_SHIFT);
  331. if( (mfn > 0) && ((mfd / mfn) > 10) )
  332. plprcr |= PLPRCR_DBRMO;
  333. plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */
  334. immr->im_clkrstk.cark_plprcrk = 0x00000000;
  335. return (n);
  336. }
  337. #endif /* CONFIG_8xx_CPUCLK_DEFAULT */