plprcr_write.S 2.2 KB

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  1. /*
  2. * (C) Copyright 2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <mpc8xx.h>
  8. #include <ppc_asm.tmpl>
  9. #include <asm/cache.h>
  10. #define CACHE_CMD_ENABLE 0x02000000
  11. #define CACHE_CMD_DISABLE 0x04000000
  12. #define CACHE_CMD_LOAD_LOCK 0x06000000
  13. #define CACHE_CMD_UNLOCK_LINE 0x08000000
  14. #define CACHE_CMD_UNLOCK_ALL 0x0A000000
  15. #define CACHE_CMD_INVALIDATE 0x0C000000
  16. #define SPEED_PLPRCR_WAIT_5CYC 150
  17. #define _CACHE_ALIGN_SIZE 16
  18. .text
  19. .align 2
  20. .globl plprcr_write_866
  21. /*
  22. * void plprcr_write_866 (long plprcr)
  23. * Write PLPRCR, including workaround for device errata SIU4 and SIU9.
  24. */
  25. plprcr_write_866:
  26. mfspr r10, LR /* save the Link Register value */
  27. /* turn instruction cache on (no MMU required for instructions)
  28. */
  29. lis r4, CACHE_CMD_ENABLE@h
  30. ori r4, r4, CACHE_CMD_ENABLE@l
  31. mtspr IC_CST, r4
  32. isync
  33. /* clear IC_CST error bits
  34. */
  35. mfspr r4, IC_CST
  36. bl plprcr_here
  37. plprcr_here:
  38. mflr r5
  39. /* calculate relocation offset
  40. */
  41. lis r4, plprcr_here@h
  42. ori r4, r4, plprcr_here@l
  43. sub r5, r5, r4
  44. /* calculate first address of this function
  45. */
  46. lis r6, plprcr_write_866@h
  47. ori r6, r6, plprcr_write_866@l
  48. add r6, r6, r5
  49. /* calculate end address of this function
  50. */
  51. lis r7, plprcr_end@h
  52. ori r7, r7, plprcr_end@l
  53. add r7, r7, r5
  54. /* load and lock code addresses
  55. */
  56. mr r5, r6
  57. plprcr_loop:
  58. mtspr IC_ADR, r5
  59. addi r5, r5, _CACHE_ALIGN_SIZE /* increment by one line */
  60. lis r4, CACHE_CMD_LOAD_LOCK@h
  61. ori r4, r4, CACHE_CMD_LOAD_LOCK@l
  62. mtspr IC_CST, r4
  63. isync
  64. cmpw r5, r7
  65. blt plprcr_loop
  66. /* IC_CST error bits not evaluated
  67. */
  68. /* switch PLPRCR
  69. */
  70. mfspr r4, IMMR /* read IMMR */
  71. rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */
  72. /* write sequence according to MPC866 Errata
  73. */
  74. stw r3, PLPRCR(r4)
  75. isync
  76. lis r3, SPEED_PLPRCR_WAIT_5CYC@h
  77. ori r3, r3, SPEED_PLPRCR_WAIT_5CYC@l
  78. plprcr_wait:
  79. cmpwi r3, 0
  80. beq plprcr_wait_end
  81. nop
  82. subi r3, r3, 1
  83. b plprcr_wait
  84. plprcr_wait_end:
  85. /* unlock instruction cache but leave it enabled
  86. */
  87. lis r4, CACHE_CMD_UNLOCK_ALL@h
  88. ori r4, r4, CACHE_CMD_UNLOCK_ALL@l
  89. mtspr IC_CST, r4
  90. isync
  91. mtspr LR, r10 /* restore original Link Register value */
  92. blr
  93. plprcr_end: