sama5d3xek.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the SAMA5D3xEK board.
  4. *
  5. * Copyright (C) 2012 - 2013 Atmel
  6. *
  7. * based on at91sam9m10g45ek.h by:
  8. * Stelian Pop <stelian@popies.net>
  9. * Lead Tech Design <www.leadtechdesign.com>
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. #include "at91-sama5_common.h"
  14. /*
  15. * This needs to be defined for the OHCI code to work but it is defined as
  16. * ATMEL_ID_UHPHS in the CPU specific header files.
  17. */
  18. #define ATMEL_ID_UHP 32
  19. /*
  20. * Specify the clock enable bit in the PMC_SCER register.
  21. */
  22. #define ATMEL_PMC_UHP (1 << 6)
  23. /* board specific (not enough SRAM) */
  24. #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
  25. /* NOR flash */
  26. #ifdef CONFIG_MTD_NOR_FLASH
  27. #define CONFIG_SYS_FLASH_BASE 0x10000000
  28. #define CONFIG_SYS_MAX_FLASH_SECT 131
  29. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  30. #endif
  31. /* SDRAM */
  32. #define CONFIG_SYS_SDRAM_BASE 0x20000000
  33. #define CONFIG_SYS_SDRAM_SIZE 0x20000000
  34. #ifdef CONFIG_SPL_BUILD
  35. #define CONFIG_SYS_INIT_SP_ADDR 0x318000
  36. #else
  37. #define CONFIG_SYS_INIT_SP_ADDR \
  38. (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  39. #endif
  40. /* SerialFlash */
  41. #ifdef CONFIG_CMD_SF
  42. #define CONFIG_SF_DEFAULT_SPEED 30000000
  43. #endif
  44. /* NAND flash */
  45. #ifdef CONFIG_CMD_NAND
  46. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  47. #define CONFIG_SYS_NAND_BASE 0x60000000
  48. /* our ALE is AD21 */
  49. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  50. /* our CLE is AD22 */
  51. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  52. #define CONFIG_SYS_NAND_ONFI_DETECTION
  53. #endif
  54. /* USB */
  55. #ifdef CONFIG_CMD_USB
  56. #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  57. #define CONFIG_USB_OHCI_NEW
  58. #define CONFIG_SYS_USB_OHCI_CPU_INIT
  59. #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
  60. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
  61. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
  62. #endif
  63. #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  64. /* SPL */
  65. #define CONFIG_SPL_TEXT_BASE 0x300000
  66. #define CONFIG_SPL_MAX_SIZE 0x18000
  67. #define CONFIG_SPL_BSS_START_ADDR 0x20000000
  68. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  69. #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
  70. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
  71. #define CONFIG_SYS_MONITOR_LEN (512 << 10)
  72. #ifdef CONFIG_SD_BOOT
  73. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  74. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  75. #elif CONFIG_SPI_BOOT
  76. #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
  77. #elif CONFIG_NAND_BOOT
  78. #define CONFIG_SPL_NAND_DRIVERS
  79. #define CONFIG_SPL_NAND_BASE
  80. #endif
  81. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  82. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  83. #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
  84. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  85. #define CONFIG_SYS_NAND_OOBSIZE 64
  86. #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
  87. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
  88. #endif