mpc837xerdb.c 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  4. * Kevin Lam <kevin.lam@freescale.com>
  5. * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <env.h>
  9. #include <hwconfig.h>
  10. #include <i2c.h>
  11. #include <init.h>
  12. #include <asm/io.h>
  13. #include <asm/fsl_mpc83xx_serdes.h>
  14. #include <fdt_support.h>
  15. #include <spd_sdram.h>
  16. #include <vsc7385.h>
  17. #include <fsl_esdhc.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #if defined(CONFIG_SYS_DRAM_TEST)
  20. int
  21. testdram(void)
  22. {
  23. uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  24. uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  25. uint *p;
  26. printf("Testing DRAM from 0x%08x to 0x%08x\n",
  27. CONFIG_SYS_MEMTEST_START,
  28. CONFIG_SYS_MEMTEST_END);
  29. printf("DRAM test phase 1:\n");
  30. for (p = pstart; p < pend; p++)
  31. *p = 0xaaaaaaaa;
  32. for (p = pstart; p < pend; p++) {
  33. if (*p != 0xaaaaaaaa) {
  34. printf("DRAM test fails at: %08x\n", (uint) p);
  35. return 1;
  36. }
  37. }
  38. printf("DRAM test phase 2:\n");
  39. for (p = pstart; p < pend; p++)
  40. *p = 0x55555555;
  41. for (p = pstart; p < pend; p++) {
  42. if (*p != 0x55555555) {
  43. printf("DRAM test fails at: %08x\n", (uint) p);
  44. return 1;
  45. }
  46. }
  47. printf("DRAM test passed.\n");
  48. return 0;
  49. }
  50. #endif
  51. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  52. void ddr_enable_ecc(unsigned int dram_size);
  53. #endif
  54. int fixed_sdram(void);
  55. int dram_init(void)
  56. {
  57. immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  58. u32 msize = 0;
  59. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  60. return -ENXIO;
  61. #if defined(CONFIG_SPD_EEPROM)
  62. msize = spd_sdram();
  63. #else
  64. msize = fixed_sdram();
  65. #endif
  66. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  67. /* Initialize DDR ECC byte */
  68. ddr_enable_ecc(msize * 1024 * 1024);
  69. #endif
  70. /* return total bus DDR size(bytes) */
  71. gd->ram_size = msize * 1024 * 1024;
  72. return 0;
  73. }
  74. #if !defined(CONFIG_SPD_EEPROM)
  75. /*************************************************************************
  76. * fixed sdram init -- doesn't use serial presence detect.
  77. ************************************************************************/
  78. int fixed_sdram(void)
  79. {
  80. immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  81. u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  82. u32 msize_log2 = __ilog2(msize);
  83. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  84. im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
  85. im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  86. udelay(50000);
  87. im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  88. udelay(1000);
  89. im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
  90. im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  91. udelay(1000);
  92. im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  93. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  94. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  95. im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  96. im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
  97. im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
  98. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  99. im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
  100. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  101. sync();
  102. udelay(1000);
  103. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  104. udelay(2000);
  105. return CONFIG_SYS_DDR_SIZE;
  106. }
  107. #endif /*!CONFIG_SYS_SPD_EEPROM */
  108. int checkboard(void)
  109. {
  110. puts("Board: Freescale MPC837xERDB\n");
  111. return 0;
  112. }
  113. int board_early_init_f(void)
  114. {
  115. #ifdef CONFIG_FSL_SERDES
  116. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  117. u32 spridr = in_be32(&immr->sysconf.spridr);
  118. /* we check only part num, and don't look for CPU revisions */
  119. switch (PARTID_NO_E(spridr)) {
  120. case SPR_8377:
  121. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
  122. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  123. fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
  124. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  125. break;
  126. case SPR_8378:
  127. fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
  128. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  129. break;
  130. case SPR_8379:
  131. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
  132. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  133. fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
  134. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  135. break;
  136. default:
  137. printf("serdes not configured: unknown CPU part number: "
  138. "%04x\n", spridr >> 16);
  139. break;
  140. }
  141. #endif /* CONFIG_FSL_SERDES */
  142. return 0;
  143. }
  144. #ifdef CONFIG_FSL_ESDHC
  145. int board_mmc_init(bd_t *bd)
  146. {
  147. struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
  148. char buffer[HWCONFIG_BUFFER_SIZE] = {0};
  149. int esdhc_hwconfig_enabled = 0;
  150. if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
  151. esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
  152. if (esdhc_hwconfig_enabled == 0)
  153. return 0;
  154. clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
  155. clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
  156. return fsl_esdhc_mmc_init(bd);
  157. }
  158. #endif
  159. /*
  160. * Miscellaneous late-boot configurations
  161. *
  162. * If a VSC7385 microcode image is present, then upload it.
  163. */
  164. int misc_init_r(void)
  165. {
  166. int rc = 0;
  167. #ifdef CONFIG_VSC7385_IMAGE
  168. if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
  169. CONFIG_VSC7385_IMAGE_SIZE)) {
  170. puts("Failure uploading VSC7385 microcode.\n");
  171. rc = 1;
  172. }
  173. #endif
  174. return rc;
  175. }
  176. #if defined(CONFIG_OF_BOARD_SETUP)
  177. int ft_board_setup(void *blob, bd_t *bd)
  178. {
  179. #ifdef CONFIG_PCI
  180. ft_pci_setup(blob, bd);
  181. #endif
  182. ft_cpu_setup(blob, bd);
  183. fsl_fdt_fixup_dr_usb(blob, bd);
  184. fdt_fixup_esdhc(blob, bd);
  185. return 0;
  186. }
  187. #endif /* CONFIG_OF_BOARD_SETUP */