P1_P2_RDB.h 20 KB

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  1. /*
  2. * Copyright 2009 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * P1 P2 RDB board configuration file
  24. * This file is intended to address a set of Low End and Ultra Low End
  25. * Freescale SOCs of QorIQ series(RDB platforms).
  26. * Currently only P2020RDB
  27. */
  28. #ifndef __CONFIG_H
  29. #define __CONFIG_H
  30. #ifdef CONFIG_MK_P1011RDB
  31. #define CONFIG_P1011
  32. #endif
  33. #ifdef CONFIG_MK_P1020RDB
  34. #define CONFIG_P1020
  35. #endif
  36. #ifdef CONFIG_MK_P2010RDB
  37. #define CONFIG_P2010
  38. #endif
  39. #ifdef CONFIG_MK_P2020RDB
  40. #define CONFIG_P2020
  41. #endif
  42. #ifdef CONFIG_MK_NAND
  43. #define CONFIG_NAND_U_BOOT 1
  44. #define CONFIG_RAMBOOT_NAND 1
  45. #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
  46. #endif
  47. #ifdef CONFIG_MK_SDCARD
  48. #define CONFIG_RAMBOOT_SDCARD 1
  49. #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
  50. #endif
  51. #ifdef CONFIG_MK_SPIFLASH
  52. #define CONFIG_RAMBOOT_SPIFLASH 1
  53. #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
  54. #endif
  55. /* High Level Configuration Options */
  56. #define CONFIG_BOOKE 1 /* BOOKE */
  57. #define CONFIG_E500 1 /* BOOKE e500 family */
  58. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
  59. #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
  60. #define CONFIG_PCI 1 /* Enable PCI/PCIE */
  61. #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
  62. #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
  63. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  64. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  65. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  66. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  67. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  68. #define CONFIG_ENV_OVERWRITE
  69. #ifndef __ASSEMBLY__
  70. extern unsigned long get_board_sys_clk(unsigned long dummy);
  71. #endif
  72. #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
  73. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
  74. #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
  75. #define CONFIG_MP
  76. #endif
  77. /*
  78. * These can be toggled for performance analysis, otherwise use default.
  79. */
  80. #define CONFIG_L2_CACHE /* toggle L2 cache */
  81. #define CONFIG_BTB /* toggle branch predition */
  82. #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
  83. #define CONFIG_ENABLE_36BIT_PHYS 1
  84. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
  85. #define CONFIG_SYS_MEMTEST_END 0x1fffffff
  86. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  87. /*
  88. * Config the L2 Cache as L2 SRAM
  89. */
  90. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  91. #ifdef CONFIG_PHYS_64BIT
  92. #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
  93. #else
  94. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  95. #endif
  96. #define CONFIG_SYS_L2_SIZE (512 << 10)
  97. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  98. /*
  99. * Base addresses -- Note these are effective addresses where the
  100. * actual resources get mapped (not physical addresses)
  101. */
  102. #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
  103. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
  104. /* CCSRBAR */
  105. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
  106. /* CONFIG_SYS_IMMR */
  107. #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
  108. #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
  109. #else
  110. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  111. #endif
  112. #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
  113. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
  114. /* DDR Setup */
  115. #define CONFIG_FSL_DDR2
  116. #undef CONFIG_FSL_DDR_INTERACTIVE
  117. #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  118. #undef CONFIG_DDR_DLL
  119. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  120. #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
  121. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  122. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  123. #define CONFIG_NUM_DDR_CONTROLLERS 1
  124. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  125. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  126. #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
  127. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  128. #define CONFIG_SYS_DDR_SBE 0x00FF0000
  129. #define CONFIG_SYS_DDR_TLB_START 9
  130. /*
  131. * Memory map
  132. *
  133. * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
  134. * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  135. * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
  136. *
  137. * Localbus cacheable (TBD)
  138. * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
  139. *
  140. * Localbus non-cacheable
  141. * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
  142. * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
  143. * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
  144. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  145. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  146. */
  147. /*
  148. * Local Bus Definitions
  149. */
  150. #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
  151. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  152. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  153. BR_PS_16 | BR_V)
  154. #define CONFIG_FLASH_OR_PRELIM 0xff000ff7
  155. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  156. #define CONFIG_SYS_FLASH_QUIET_TEST
  157. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  158. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  159. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  160. #undef CONFIG_SYS_FLASH_CHECKSUM
  161. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  162. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  163. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  164. #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
  165. || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
  166. #define CONFIG_SYS_RAMBOOT
  167. #else
  168. #undef CONFIG_SYS_RAMBOOT
  169. #endif
  170. #define CONFIG_FLASH_CFI_DRIVER
  171. #define CONFIG_SYS_FLASH_CFI
  172. #define CONFIG_SYS_FLASH_EMPTY_INFO
  173. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  174. #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  175. #define CONFIG_SYS_INIT_RAM_LOCK 1
  176. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  177. #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
  178. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  179. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
  180. - CONFIG_SYS_GBL_DATA_SIZE)
  181. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  182. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
  183. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
  184. #ifndef CONFIG_NAND_SPL
  185. #define CONFIG_SYS_NAND_BASE 0xffa00000
  186. #else
  187. #define CONFIG_SYS_NAND_BASE 0xfff00000
  188. #endif
  189. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  190. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  191. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  192. #define NAND_MAX_CHIPS 1
  193. #define CONFIG_MTD_NAND_VERIFY_WRITE
  194. #define CONFIG_CMD_NAND 1
  195. #define CONFIG_NAND_FSL_ELBC 1
  196. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
  197. /* NAND boot: 4K NAND loader config */
  198. #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
  199. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
  200. #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
  201. #define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
  202. #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
  203. #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
  204. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  205. /* NAND flash config */
  206. #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
  207. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  208. | BR_PS_8 /* Port Size = 8 bit */ \
  209. | BR_MS_FCM /* MSEL = FCM */ \
  210. | BR_V) /* valid */
  211. #define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
  212. | OR_FCM_CSCT \
  213. | OR_FCM_CST \
  214. | OR_FCM_CHT \
  215. | OR_FCM_SCY_1 \
  216. | OR_FCM_TRLX \
  217. | OR_FCM_EHTR)
  218. #ifdef CONFIG_RAMBOOT_NAND
  219. #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
  220. #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  221. #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  222. #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  223. #else
  224. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  225. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  226. #define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
  227. #define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  228. #endif
  229. #define CONFIG_SYS_VSC7385_BASE 0xffb00000
  230. #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
  231. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
  232. #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
  233. OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
  234. OR_GPCM_EHTR | OR_GPCM_EAD)
  235. /* Serial Port - controlled on board with jumper J8
  236. * open - index 2
  237. * shorted - index 1
  238. */
  239. #define CONFIG_CONS_INDEX 1
  240. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  241. #define CONFIG_SYS_NS16550
  242. #define CONFIG_SYS_NS16550_SERIAL
  243. #define CONFIG_SYS_NS16550_REG_SIZE 1
  244. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  245. #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
  246. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
  247. #define CONFIG_SYS_BAUDRATE_TABLE \
  248. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  249. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  250. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  251. /* Use the HUSH parser */
  252. #define CONFIG_SYS_HUSH_PARSER
  253. #ifdef CONFIG_SYS_HUSH_PARSER
  254. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  255. #endif
  256. /*
  257. * Pass open firmware flat tree
  258. */
  259. #define CONFIG_OF_LIBFDT 1
  260. #define CONFIG_OF_BOARD_SETUP 1
  261. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  262. #define CONFIG_SYS_64BIT_VSPRINTF 1
  263. #define CONFIG_SYS_64BIT_STRTOUL 1
  264. /* new uImage format support */
  265. #define CONFIG_FIT 1
  266. #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
  267. /* I2C */
  268. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  269. #define CONFIG_HARD_I2C /* I2C with hardware support */
  270. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  271. #define CONFIG_I2C_MULTI_BUS
  272. #define CONFIG_I2C_CMD_TREE
  273. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
  274. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  275. #define CONFIG_SYS_I2C_SLAVE 0x7F
  276. #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
  277. #define CONFIG_SYS_I2C_OFFSET 0x3000
  278. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  279. /*
  280. * I2C2 EEPROM
  281. */
  282. #define CONFIG_ID_EEPROM
  283. #ifdef CONFIG_ID_EEPROM
  284. #define CONFIG_SYS_I2C_EEPROM_NXID
  285. #endif
  286. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  287. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  288. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  289. #define CONFIG_RTC_DS1337
  290. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  291. /*
  292. * General PCI
  293. * Memory space is mapped 1-1, but I/O space must start from 0.
  294. */
  295. /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  296. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  297. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  298. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  299. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  300. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
  301. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  302. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
  303. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  304. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  305. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  306. #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
  307. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
  308. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  309. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
  310. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  311. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
  312. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  313. #if defined(CONFIG_PCI)
  314. #define CONFIG_NET_MULTI
  315. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  316. #undef CONFIG_EEPRO100
  317. #undef CONFIG_TULIP
  318. #undef CONFIG_RTL8139
  319. #ifdef CONFIG_RTL8139
  320. /* This macro is used by RTL8139 but not defined in PPC architecture */
  321. #define KSEG1ADDR(x) (x)
  322. #define _IO_BASE 0x00000000
  323. #endif
  324. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  325. #define CONFIG_DOS_PARTITION
  326. #endif /* CONFIG_PCI */
  327. #if defined(CONFIG_TSEC_ENET)
  328. #ifndef CONFIG_NET_MULTI
  329. #define CONFIG_NET_MULTI 1
  330. #endif
  331. #define CONFIG_MII 1 /* MII PHY management */
  332. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  333. #define CONFIG_TSEC1 1
  334. #define CONFIG_TSEC1_NAME "eTSEC1"
  335. #define CONFIG_TSEC2 1
  336. #define CONFIG_TSEC2_NAME "eTSEC2"
  337. #define CONFIG_TSEC3 1
  338. #define CONFIG_TSEC3_NAME "eTSEC3"
  339. #define TSEC1_PHY_ADDR 2
  340. #define TSEC2_PHY_ADDR 0
  341. #define TSEC3_PHY_ADDR 1
  342. #define CONFIG_VSC7385_ENET
  343. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  344. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  345. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  346. #define TSEC1_PHYIDX 0
  347. #define TSEC2_PHYIDX 0
  348. #define TSEC3_PHYIDX 0
  349. /* Vitesse 7385 */
  350. #ifdef CONFIG_VSC7385_ENET
  351. /* The size of the VSC7385 firmware image */
  352. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  353. #endif
  354. #define CONFIG_ETHPRIME "eTSEC1"
  355. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  356. #endif /* CONFIG_TSEC_ENET */
  357. /*
  358. * Environment
  359. */
  360. #if defined(CONFIG_SYS_RAMBOOT)
  361. #if defined(CONFIG_RAMBOOT_NAND)
  362. #define CONFIG_ENV_IS_IN_NAND 1
  363. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  364. #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
  365. #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
  366. #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  367. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  368. #define CONFIG_ENV_SIZE 0x2000
  369. #endif
  370. #else
  371. #define CONFIG_ENV_IS_IN_FLASH 1
  372. #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
  373. #define CONFIG_ENV_ADDR 0xfff80000
  374. #else
  375. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  376. #endif
  377. #define CONFIG_ENV_SIZE 0x2000
  378. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  379. #endif
  380. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  381. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  382. /*
  383. * Command line configuration.
  384. */
  385. #include <config_cmd_default.h>
  386. #define CONFIG_CMD_DATE
  387. #define CONFIG_CMD_ELF
  388. #define CONFIG_CMD_I2C
  389. #define CONFIG_CMD_IRQ
  390. #define CONFIG_CMD_MII
  391. #define CONFIG_CMD_PING
  392. #define CONFIG_CMD_SETEXPR
  393. #if defined(CONFIG_PCI)
  394. #define CONFIG_CMD_NET
  395. #define CONFIG_CMD_PCI
  396. #endif
  397. #undef CONFIG_WATCHDOG /* watchdog disabled */
  398. #define CONFIG_MMC 1
  399. #ifdef CONFIG_MMC
  400. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  401. #define CONFIG_CMD_MMC
  402. #define CONFIG_DOS_PARTITION
  403. #define CONFIG_FSL_ESDHC
  404. #define CONFIG_GENERIC_MMC
  405. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  406. #ifdef CONFIG_P2020
  407. #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
  408. #endif
  409. #endif
  410. #define CONFIG_USB_EHCI
  411. #ifdef CONFIG_USB_EHCI
  412. #define CONFIG_CMD_USB
  413. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  414. #define CONFIG_USB_EHCI_FSL
  415. #define CONFIG_USB_STORAGE
  416. #endif
  417. #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
  418. #define CONFIG_CMD_EXT2
  419. #define CONFIG_CMD_FAT
  420. #define CONFIG_DOS_PARTITION
  421. #endif
  422. /*
  423. * Miscellaneous configurable options
  424. */
  425. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  426. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  427. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  428. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  429. #if defined(CONFIG_CMD_KGDB)
  430. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  431. #else
  432. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  433. #endif
  434. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  435. /* Print Buffer Size */
  436. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  437. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  438. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  439. /*
  440. * For booting Linux, the board info and command line data
  441. * have to be in the first 16 MB of memory, since this is
  442. * the maximum mapped by the Linux kernel during initialization.
  443. */
  444. #define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/
  445. /*
  446. * Internal Definitions
  447. *
  448. * Boot Flags
  449. */
  450. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  451. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  452. #if defined(CONFIG_CMD_KGDB)
  453. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  454. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  455. #endif
  456. /*
  457. * Environment Configuration
  458. */
  459. #if defined(CONFIG_TSEC_ENET)
  460. #define CONFIG_HAS_ETH0
  461. #define CONFIG_HAS_ETH1
  462. #define CONFIG_HAS_ETH2
  463. #endif
  464. #define CONFIG_HOSTNAME P2020RDB
  465. #define CONFIG_ROOTPATH /opt/nfsroot
  466. #define CONFIG_BOOTFILE uImage
  467. #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
  468. /* default location for tftp and bootm */
  469. #define CONFIG_LOADADDR 1000000
  470. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  471. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  472. #define CONFIG_BAUDRATE 115200
  473. #define CONFIG_EXTRA_ENV_SETTINGS \
  474. "netdev=eth0\0" \
  475. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  476. "loadaddr=1000000\0" \
  477. "bootfile=uImage\0" \
  478. "tftpflash=tftpboot $loadaddr $uboot; " \
  479. "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
  480. "erase " MK_STR(TEXT_BASE) " +$filesize; " \
  481. "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
  482. "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
  483. "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
  484. "consoledev=ttyS0\0" \
  485. "ramdiskaddr=2000000\0" \
  486. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  487. "fdtaddr=c00000\0" \
  488. "fdtfile=p2020rdb.dtb\0" \
  489. "bdev=sda1\0" \
  490. "jffs2nor=mtdblock3\0" \
  491. "norbootaddr=ef080000\0" \
  492. "norfdtaddr=ef040000\0" \
  493. "jffs2nand=mtdblock9\0" \
  494. "nandbootaddr=100000\0" \
  495. "nandfdtaddr=80000\0" \
  496. "nandimgsize=400000\0" \
  497. "nandfdtsize=80000\0" \
  498. "usb_phy_type=ulpi\0" \
  499. "vscfw_addr=ef000000\0" \
  500. "othbootargs=ramdisk_size=600000\0" \
  501. "usbfatboot=setenv bootargs root=/dev/ram rw " \
  502. "console=$consoledev,$baudrate $othbootargs; " \
  503. "usb start;" \
  504. "fatload usb 0:2 $loadaddr $bootfile;" \
  505. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  506. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  507. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  508. "usbext2boot=setenv bootargs root=/dev/ram rw " \
  509. "console=$consoledev,$baudrate $othbootargs; " \
  510. "usb start;" \
  511. "ext2load usb 0:4 $loadaddr $bootfile;" \
  512. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  513. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  514. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  515. "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
  516. "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
  517. "bootm $norbootaddr - $norfdtaddr\0" \
  518. "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
  519. "console=$consoledev,$baudrate $othbootargs;" \
  520. "nand read 2000000 $nandbootaddr $nandimgsize;" \
  521. "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
  522. "bootm 2000000 - 3000000;\0"
  523. #define CONFIG_NFSBOOTCOMMAND \
  524. "setenv bootargs root=/dev/nfs rw " \
  525. "nfsroot=$serverip:$rootpath " \
  526. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  527. "console=$consoledev,$baudrate $othbootargs;" \
  528. "tftp $loadaddr $bootfile;" \
  529. "tftp $fdtaddr $fdtfile;" \
  530. "bootm $loadaddr - $fdtaddr"
  531. #define CONFIG_HDBOOT \
  532. "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  533. "console=$consoledev,$baudrate $othbootargs;" \
  534. "usb start;" \
  535. "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  536. "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  537. "bootm $loadaddr - $fdtaddr"
  538. #define CONFIG_RAMBOOTCOMMAND \
  539. "setenv bootargs root=/dev/ram rw " \
  540. "console=$consoledev,$baudrate $othbootargs; " \
  541. "tftp $ramdiskaddr $ramdiskfile;" \
  542. "tftp $loadaddr $bootfile;" \
  543. "tftp $fdtaddr $fdtfile;" \
  544. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  545. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  546. #endif /* __CONFIG_H */