miiphybb.c 8.1 KB

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  1. /*
  2. * (C) Copyright 2009 Industrie Dial Face S.p.A.
  3. * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
  4. *
  5. * (C) Copyright 2001
  6. * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. * This provides a bit-banged interface to the ethernet MII management
  28. * channel.
  29. */
  30. #include <common.h>
  31. #include <ioports.h>
  32. #include <ppc_asm.tmpl>
  33. #include <miiphy.h>
  34. #define BB_MII_RELOCATE(v,off) (v += (v?off:0))
  35. DECLARE_GLOBAL_DATA_PTR;
  36. #ifndef CONFIG_BITBANGMII_MULTI
  37. /*
  38. * If CONFIG_BITBANGMII_MULTI is not defined we use a
  39. * compatibility layer with the previous miiphybb implementation
  40. * based on macros usage.
  41. *
  42. */
  43. static int bb_mii_init_wrap(struct bb_miiphy_bus *bus)
  44. {
  45. #ifdef MII_INIT
  46. MII_INIT;
  47. #endif
  48. return 0;
  49. }
  50. static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus)
  51. {
  52. #ifdef MDIO_DECLARE
  53. MDIO_DECLARE;
  54. #endif
  55. MDIO_ACTIVE;
  56. return 0;
  57. }
  58. static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus)
  59. {
  60. #ifdef MDIO_DECLARE
  61. MDIO_DECLARE;
  62. #endif
  63. MDIO_TRISTATE;
  64. return 0;
  65. }
  66. static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v)
  67. {
  68. #ifdef MDIO_DECLARE
  69. MDIO_DECLARE;
  70. #endif
  71. MDIO(v);
  72. return 0;
  73. }
  74. static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v)
  75. {
  76. #ifdef MDIO_DECLARE
  77. MDIO_DECLARE;
  78. #endif
  79. *v = MDIO_READ;
  80. return 0;
  81. }
  82. static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v)
  83. {
  84. #ifdef MDC_DECLARE
  85. MDC_DECLARE;
  86. #endif
  87. MDC(v);
  88. return 0;
  89. }
  90. static int bb_delay_wrap(struct bb_miiphy_bus *bus)
  91. {
  92. MIIDELAY;
  93. return 0;
  94. }
  95. struct bb_miiphy_bus bb_miiphy_buses[] = {
  96. {
  97. .name = BB_MII_DEVNAME,
  98. .init = bb_mii_init_wrap,
  99. .mdio_active = bb_mdio_active_wrap,
  100. .mdio_tristate = bb_mdio_tristate_wrap,
  101. .set_mdio = bb_set_mdio_wrap,
  102. .get_mdio = bb_get_mdio_wrap,
  103. .set_mdc = bb_set_mdc_wrap,
  104. .delay = bb_delay_wrap,
  105. }
  106. };
  107. int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
  108. sizeof(bb_miiphy_buses[0]);
  109. #endif
  110. void bb_miiphy_init(void)
  111. {
  112. int i;
  113. for (i = 0; i < bb_miiphy_buses_num; i++) {
  114. #if !defined(CONFIG_RELOC_FIXUP_WORKS)
  115. /* Relocate the hook pointers*/
  116. BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off);
  117. BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off);
  118. BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off);
  119. BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off);
  120. BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off);
  121. BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off);
  122. BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off);
  123. #endif
  124. if (bb_miiphy_buses[i].init != NULL) {
  125. bb_miiphy_buses[i].init(&bb_miiphy_buses[i]);
  126. }
  127. }
  128. }
  129. static inline struct bb_miiphy_bus *bb_miiphy_getbus(char *devname)
  130. {
  131. #ifdef CONFIG_BITBANGMII_MULTI
  132. int i;
  133. /* Search the correct bus */
  134. for (i = 0; i < bb_miiphy_buses_num; i++) {
  135. if (!strcmp(bb_miiphy_buses[i].name, devname)) {
  136. return &bb_miiphy_buses[i];
  137. }
  138. }
  139. return NULL;
  140. #else
  141. /* We have just one bitbanging bus */
  142. return &bb_miiphy_buses[0];
  143. #endif
  144. }
  145. /*****************************************************************************
  146. *
  147. * Utility to send the preamble, address, and register (common to read
  148. * and write).
  149. */
  150. static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
  151. unsigned char addr, unsigned char reg)
  152. {
  153. int j;
  154. /*
  155. * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
  156. * The IEEE spec says this is a PHY optional requirement. The AMD
  157. * 79C874 requires one after power up and one after a MII communications
  158. * error. This means that we are doing more preambles than we need,
  159. * but it is safer and will be much more robust.
  160. */
  161. bus->mdio_active(bus);
  162. bus->set_mdio(bus, 1);
  163. for (j = 0; j < 32; j++) {
  164. bus->set_mdc(bus, 0);
  165. bus->delay(bus);
  166. bus->set_mdc(bus, 1);
  167. bus->delay(bus);
  168. }
  169. /* send the start bit (01) and the read opcode (10) or write (10) */
  170. bus->set_mdc(bus, 0);
  171. bus->set_mdio(bus, 0);
  172. bus->delay(bus);
  173. bus->set_mdc(bus, 1);
  174. bus->delay(bus);
  175. bus->set_mdc(bus, 0);
  176. bus->set_mdio(bus, 1);
  177. bus->delay(bus);
  178. bus->set_mdc(bus, 1);
  179. bus->delay(bus);
  180. bus->set_mdc(bus, 0);
  181. bus->set_mdio(bus, read);
  182. bus->delay(bus);
  183. bus->set_mdc(bus, 1);
  184. bus->delay(bus);
  185. bus->set_mdc(bus, 0);
  186. bus->set_mdio(bus, !read);
  187. bus->delay(bus);
  188. bus->set_mdc(bus, 1);
  189. bus->delay(bus);
  190. /* send the PHY address */
  191. for (j = 0; j < 5; j++) {
  192. bus->set_mdc(bus, 0);
  193. if ((addr & 0x10) == 0) {
  194. bus->set_mdio(bus, 0);
  195. } else {
  196. bus->set_mdio(bus, 1);
  197. }
  198. bus->delay(bus);
  199. bus->set_mdc(bus, 1);
  200. bus->delay(bus);
  201. addr <<= 1;
  202. }
  203. /* send the register address */
  204. for (j = 0; j < 5; j++) {
  205. bus->set_mdc(bus, 0);
  206. if ((reg & 0x10) == 0) {
  207. bus->set_mdio(bus, 0);
  208. } else {
  209. bus->set_mdio(bus, 1);
  210. }
  211. bus->delay(bus);
  212. bus->set_mdc(bus, 1);
  213. bus->delay(bus);
  214. reg <<= 1;
  215. }
  216. }
  217. /*****************************************************************************
  218. *
  219. * Read a MII PHY register.
  220. *
  221. * Returns:
  222. * 0 on success
  223. */
  224. int bb_miiphy_read(char *devname, unsigned char addr,
  225. unsigned char reg, unsigned short *value)
  226. {
  227. short rdreg; /* register working value */
  228. int v;
  229. int j; /* counter */
  230. struct bb_miiphy_bus *bus;
  231. bus = bb_miiphy_getbus(devname);
  232. if (bus == NULL) {
  233. return -1;
  234. }
  235. if (value == NULL) {
  236. puts("NULL value pointer\n");
  237. return -1;
  238. }
  239. miiphy_pre (bus, 1, addr, reg);
  240. /* tri-state our MDIO I/O pin so we can read */
  241. bus->set_mdc(bus, 0);
  242. bus->mdio_tristate(bus);
  243. bus->delay(bus);
  244. bus->set_mdc(bus, 1);
  245. bus->delay(bus);
  246. /* check the turnaround bit: the PHY should be driving it to zero */
  247. bus->get_mdio(bus, &v);
  248. if (v != 0) {
  249. /* puts ("PHY didn't drive TA low\n"); */
  250. for (j = 0; j < 32; j++) {
  251. bus->set_mdc(bus, 0);
  252. bus->delay(bus);
  253. bus->set_mdc(bus, 1);
  254. bus->delay(bus);
  255. }
  256. /* There is no PHY, set value to 0xFFFF and return */
  257. *value = 0xFFFF;
  258. return -1;
  259. }
  260. bus->set_mdc(bus, 0);
  261. bus->delay(bus);
  262. /* read 16 bits of register data, MSB first */
  263. rdreg = 0;
  264. for (j = 0; j < 16; j++) {
  265. bus->set_mdc(bus, 1);
  266. bus->delay(bus);
  267. rdreg <<= 1;
  268. bus->get_mdio(bus, &v);
  269. rdreg |= (v & 0x1);
  270. bus->set_mdc(bus, 0);
  271. bus->delay(bus);
  272. }
  273. bus->set_mdc(bus, 1);
  274. bus->delay(bus);
  275. bus->set_mdc(bus, 0);
  276. bus->delay(bus);
  277. bus->set_mdc(bus, 1);
  278. bus->delay(bus);
  279. *value = rdreg;
  280. #ifdef DEBUG
  281. printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
  282. #endif
  283. return 0;
  284. }
  285. /*****************************************************************************
  286. *
  287. * Write a MII PHY register.
  288. *
  289. * Returns:
  290. * 0 on success
  291. */
  292. int bb_miiphy_write (char *devname, unsigned char addr,
  293. unsigned char reg, unsigned short value)
  294. {
  295. struct bb_miiphy_bus *bus;
  296. int j; /* counter */
  297. bus = bb_miiphy_getbus(devname);
  298. if (bus == NULL) {
  299. /* Bus not found! */
  300. return -1;
  301. }
  302. miiphy_pre (bus, 0, addr, reg);
  303. /* send the turnaround (10) */
  304. bus->set_mdc(bus, 0);
  305. bus->set_mdio(bus, 1);
  306. bus->delay(bus);
  307. bus->set_mdc(bus, 1);
  308. bus->delay(bus);
  309. bus->set_mdc(bus, 0);
  310. bus->set_mdio(bus, 0);
  311. bus->delay(bus);
  312. bus->set_mdc(bus, 1);
  313. bus->delay(bus);
  314. /* write 16 bits of register data, MSB first */
  315. for (j = 0; j < 16; j++) {
  316. bus->set_mdc(bus, 0);
  317. if ((value & 0x00008000) == 0) {
  318. bus->set_mdio(bus, 0);
  319. } else {
  320. bus->set_mdio(bus, 1);
  321. }
  322. bus->delay(bus);
  323. bus->set_mdc(bus, 1);
  324. bus->delay(bus);
  325. value <<= 1;
  326. }
  327. /*
  328. * Tri-state the MDIO line.
  329. */
  330. bus->mdio_tristate(bus);
  331. bus->set_mdc(bus, 0);
  332. bus->delay(bus);
  333. bus->set_mdc(bus, 1);
  334. bus->delay(bus);
  335. return 0;
  336. }