reset_manager_s10.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/reset_manager.h>
  9. #include <asm/arch/system_manager.h>
  10. #include <dt-bindings/reset/altr,rst-mgr-s10.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. static const struct socfpga_reset_manager *reset_manager_base =
  13. (void *)SOCFPGA_RSTMGR_ADDRESS;
  14. static const struct socfpga_system_manager *system_manager_base =
  15. (void *)SOCFPGA_SYSMGR_ADDRESS;
  16. /* Assert or de-assert SoCFPGA reset manager reset. */
  17. void socfpga_per_reset(u32 reset, int set)
  18. {
  19. const void *reg;
  20. if (RSTMGR_BANK(reset) == 0)
  21. reg = &reset_manager_base->mpumodrst;
  22. else if (RSTMGR_BANK(reset) == 1)
  23. reg = &reset_manager_base->per0modrst;
  24. else if (RSTMGR_BANK(reset) == 2)
  25. reg = &reset_manager_base->per1modrst;
  26. else if (RSTMGR_BANK(reset) == 3)
  27. reg = &reset_manager_base->brgmodrst;
  28. else /* Invalid reset register, do nothing */
  29. return;
  30. if (set)
  31. setbits_le32(reg, 1 << RSTMGR_RESET(reset));
  32. else
  33. clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
  34. }
  35. /*
  36. * Assert reset on every peripheral but L4WD0.
  37. * Watchdog must be kept intact to prevent glitches
  38. * and/or hangs.
  39. */
  40. void socfpga_per_reset_all(void)
  41. {
  42. const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
  43. /* disable all except OCP and l4wd0. OCP disable later */
  44. writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
  45. &reset_manager_base->per0modrst);
  46. writel(~l4wd0, &reset_manager_base->per0modrst);
  47. writel(0xffffffff, &reset_manager_base->per1modrst);
  48. }
  49. void socfpga_bridges_reset(int enable)
  50. {
  51. if (enable) {
  52. /* clear idle request to all bridges */
  53. setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
  54. /* Release all bridges from reset state */
  55. clrbits_le32(&reset_manager_base->brgmodrst, ~0);
  56. /* Poll until all idleack to 0 */
  57. while (readl(&system_manager_base->noc_idleack))
  58. ;
  59. } else {
  60. /* set idle request to all bridges */
  61. writel(~0, &system_manager_base->noc_idlereq_set);
  62. /* Enable the NOC timeout */
  63. writel(1, &system_manager_base->noc_timeout);
  64. /* Poll until all idleack to 1 */
  65. while ((readl(&system_manager_base->noc_idleack) ^
  66. (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
  67. ;
  68. /* Poll until all idlestatus to 1 */
  69. while ((readl(&system_manager_base->noc_idlestatus) ^
  70. (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
  71. ;
  72. /* Reset all bridges (except NOR DDR scheduler & F2S) */
  73. setbits_le32(&reset_manager_base->brgmodrst,
  74. ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
  75. RSTMGR_BRGMODRST_FPGA2SOC_MASK));
  76. /* Disable NOC timeout */
  77. writel(0, &system_manager_base->noc_timeout);
  78. }
  79. }
  80. /*
  81. * Return non-zero if the CPU has been warm reset
  82. */
  83. int cpu_has_been_warmreset(void)
  84. {
  85. return readl(&reset_manager_base->status) &
  86. RSTMGR_L4WD_MPU_WARMRESET_MASK;
  87. }