igep00x0.h 10 KB

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  1. /*
  2. * Common configuration settings for IGEP technology based boards
  3. *
  4. * (C) Copyright 2012
  5. * ISEE 2007 SL, <www.iseebcn.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef __IGEP00X0_H
  10. #define __IGEP00X0_H
  11. #include <asm/sizes.h>
  12. /*
  13. * High Level Configuration Options
  14. */
  15. #define CONFIG_OMAP 1 /* in a TI OMAP core */
  16. #define CONFIG_OMAP34XX 1 /* which is a 34XX */
  17. #define CONFIG_OMAP_GPIO
  18. #define CONFIG_OMAP_COMMON
  19. #define CONFIG_SDRC /* The chip has SDRC controller */
  20. #include <asm/arch/cpu.h>
  21. #include <asm/arch/omap3.h>
  22. #include <asm/mach-types.h>
  23. /*
  24. * Display CPU and Board information
  25. */
  26. #define CONFIG_DISPLAY_CPUINFO 1
  27. #define CONFIG_DISPLAY_BOARDINFO 1
  28. /* Clock Defines */
  29. #define V_OSCK 26000000 /* Clock output from T2 */
  30. #define V_SCLK (V_OSCK >> 1)
  31. #define CONFIG_MISC_INIT_R
  32. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  33. #define CONFIG_SETUP_MEMORY_TAGS 1
  34. #define CONFIG_INITRD_TAG 1
  35. #define CONFIG_REVISION_TAG 1
  36. #define CONFIG_OF_LIBFDT
  37. #define CONFIG_CMD_BOOTZ
  38. #define CONFIG_SUPPORT_RAW_INITRD
  39. /*
  40. * NS16550 Configuration
  41. */
  42. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  43. #define CONFIG_SYS_NS16550
  44. #define CONFIG_SYS_NS16550_SERIAL
  45. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  46. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  47. /* select serial console configuration */
  48. #define CONFIG_CONS_INDEX 3
  49. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  50. #define CONFIG_SERIAL3 3
  51. /* allow to overwrite serial and ethaddr */
  52. #define CONFIG_ENV_OVERWRITE
  53. #define CONFIG_BAUDRATE 115200
  54. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
  55. 115200}
  56. #define CONFIG_GENERIC_MMC 1
  57. #define CONFIG_MMC 1
  58. #define CONFIG_OMAP_HSMMC 1
  59. #define CONFIG_DOS_PARTITION 1
  60. /* define to enable boot progress via leds */
  61. #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
  62. (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
  63. #define CONFIG_SHOW_BOOT_PROGRESS
  64. #endif
  65. /* USB */
  66. #define CONFIG_MUSB_UDC 1
  67. #define CONFIG_USB_OMAP3 1
  68. #define CONFIG_TWL4030_USB 1
  69. /* USB device configuration */
  70. #define CONFIG_USB_DEVICE 1
  71. #define CONFIG_USB_TTY 1
  72. #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
  73. /* Change these to suit your needs */
  74. #define CONFIG_USBD_VENDORID 0x0451
  75. #define CONFIG_USBD_PRODUCTID 0x5678
  76. #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
  77. #define CONFIG_USBD_PRODUCT_NAME "IGEP"
  78. /* commands to include */
  79. #include <config_cmd_default.h>
  80. #define CONFIG_CMD_CACHE
  81. #define CONFIG_CMD_EXT4
  82. #define CONFIG_CMD_FAT /* FAT support */
  83. #define CONFIG_CMD_FS_GENERIC
  84. #define CONFIG_CMD_I2C /* I2C serial bus support */
  85. #define CONFIG_CMD_MMC /* MMC support */
  86. #ifdef CONFIG_BOOT_ONENAND
  87. #define CONFIG_CMD_ONENAND /* ONENAND support */
  88. #endif
  89. #ifdef CONFIG_BOOT_NAND
  90. #define CONFIG_CMD_NAND
  91. #endif
  92. #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
  93. (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
  94. #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
  95. #endif
  96. #define CONFIG_CMD_DHCP
  97. #define CONFIG_CMD_PING
  98. #define CONFIG_CMD_NFS /* NFS support */
  99. #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
  100. #define CONFIG_MTD_DEVICE
  101. #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
  102. #undef CONFIG_CMD_IMLS /* List all found images */
  103. #define CONFIG_SYS_NO_FLASH
  104. #define CONFIG_HARD_I2C 1
  105. #define CONFIG_SYS_I2C_SPEED 100000
  106. #define CONFIG_SYS_I2C_SLAVE 1
  107. #define CONFIG_DRIVER_OMAP34XX_I2C 1
  108. /*
  109. * TWL4030
  110. */
  111. #define CONFIG_TWL4030_POWER 1
  112. #define CONFIG_BOOTDELAY 3
  113. #define CONFIG_EXTRA_ENV_SETTINGS \
  114. "usbtty=cdc_acm\0" \
  115. "loadaddr=0x82000000\0" \
  116. "dtbaddr=0x81600000\0" \
  117. "bootdir=/boot\0" \
  118. "bootfile=zImage\0" \
  119. "usbtty=cdc_acm\0" \
  120. "console=ttyO2,115200n8\0" \
  121. "mpurate=auto\0" \
  122. "vram=12M\0" \
  123. "dvimode=1024x768MR-16@60\0" \
  124. "defaultdisplay=dvi\0" \
  125. "mmcdev=0\0" \
  126. "mmcroot=/dev/mmcblk0p2 rw\0" \
  127. "mmcrootfstype=ext4 rootwait\0" \
  128. "nandroot=/dev/mtdblock4 rw\0" \
  129. "nandrootfstype=jffs2\0" \
  130. "mmcargs=setenv bootargs console=${console} " \
  131. "mpurate=${mpurate} " \
  132. "vram=${vram} " \
  133. "omapfb.mode=dvi:${dvimode} " \
  134. "omapfb.debug=y " \
  135. "omapdss.def_disp=${defaultdisplay} " \
  136. "root=${mmcroot} " \
  137. "rootfstype=${mmcrootfstype}\0" \
  138. "nandargs=setenv bootargs console=${console} " \
  139. "mpurate=${mpurate} " \
  140. "vram=${vram} " \
  141. "omapfb.mode=dvi:${dvimode} " \
  142. "omapfb.debug=y " \
  143. "omapdss.def_disp=${defaultdisplay} " \
  144. "root=${nandroot} " \
  145. "rootfstype=${nandrootfstype}\0" \
  146. "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
  147. "importbootenv=echo Importing environment from mmc ...; " \
  148. "env import -t $loadaddr $filesize\0" \
  149. "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
  150. "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
  151. "mmcboot=echo Booting from mmc ...; " \
  152. "run mmcargs; " \
  153. "bootz ${loadaddr}\0" \
  154. "mmcbootfdt=echo Booting with DT from mmc ...; " \
  155. "bootz ${loadaddr} - ${dtbaddr}\0" \
  156. "nandboot=echo Booting from onenand ...; " \
  157. "run nandargs; " \
  158. "onenand read ${loadaddr} 280000 400000; " \
  159. "bootz ${loadaddr}\0" \
  160. #define CONFIG_BOOTCOMMAND \
  161. "mmc dev ${mmcdev}; if mmc rescan; then " \
  162. "echo SD/MMC found on device ${mmcdev};" \
  163. "if run loadbootenv; then " \
  164. "run importbootenv;" \
  165. "fi;" \
  166. "if test -n $uenvcmd; then " \
  167. "echo Running uenvcmd ...;" \
  168. "run uenvcmd;" \
  169. "fi;" \
  170. "if run loadzimage; then " \
  171. "if test -n $dtbfile; then " \
  172. "if run loadfdt; then " \
  173. "run mmcbootfdt;" \
  174. "fi;" \
  175. "fi;" \
  176. "run mmcboot;" \
  177. "fi;" \
  178. "fi;" \
  179. "run nandboot;" \
  180. #define CONFIG_AUTO_COMPLETE 1
  181. /*
  182. * Miscellaneous configurable options
  183. */
  184. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  185. #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  186. #define CONFIG_SYS_PROMPT "U-Boot # "
  187. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  188. /* Print Buffer Size */
  189. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  190. sizeof(CONFIG_SYS_PROMPT) + 16)
  191. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  192. /* Boot Argument Buffer Size */
  193. #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  194. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
  195. /* works on */
  196. #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
  197. 0x01F00000) /* 31MB */
  198. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
  199. /* load address */
  200. #define CONFIG_SYS_MONITOR_LEN (256 << 10)
  201. /*
  202. * OMAP3 has 12 GP timers, they can be driven by the system clock
  203. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  204. * This rate is divided by a local divisor.
  205. */
  206. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  207. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  208. #define CONFIG_SYS_HZ 1000
  209. /*
  210. * Physical Memory Map
  211. *
  212. */
  213. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  214. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  215. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  216. /*
  217. * FLASH and environment organization
  218. */
  219. #ifdef CONFIG_BOOT_ONENAND
  220. #define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
  221. #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
  222. #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
  223. #define CONFIG_ENV_IS_IN_ONENAND 1
  224. #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
  225. #define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
  226. #endif
  227. #ifdef CONFIG_BOOT_NAND
  228. #define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
  229. #define CONFIG_NAND_OMAP_GPMC
  230. #define CONFIG_SYS_NAND_BASE NAND_BASE
  231. #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
  232. #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
  233. #define CONFIG_ENV_IS_IN_NAND 1
  234. #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
  235. #define CONFIG_ENV_ADDR NAND_ENV_OFFSET
  236. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  237. #endif
  238. /*
  239. * Size of malloc() pool
  240. */
  241. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  242. /*
  243. * SMSC911x Ethernet
  244. */
  245. #if defined(CONFIG_CMD_NET)
  246. #define CONFIG_SMC911X
  247. #define CONFIG_SMC911X_32_BIT
  248. #define CONFIG_SMC911X_BASE 0x2C000000
  249. #endif /* (CONFIG_CMD_NET) */
  250. /*
  251. * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
  252. * and older u-boot.bin with the new U-Boot SPL.
  253. */
  254. #define CONFIG_SYS_TEXT_BASE 0x80008000
  255. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  256. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  257. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  258. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  259. CONFIG_SYS_INIT_RAM_SIZE - \
  260. GENERATED_GBL_DATA_SIZE)
  261. /* SPL */
  262. #define CONFIG_SPL
  263. #define CONFIG_SPL_FRAMEWORK
  264. #define CONFIG_SPL_NAND_SIMPLE
  265. #define CONFIG_SPL_TEXT_BASE 0x40200800
  266. #define CONFIG_SPL_MAX_SIZE (54 * 1024)
  267. #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
  268. /* move malloc and bss high to prevent clashing with the main image */
  269. #define CONFIG_SYS_SPL_MALLOC_START 0x87000000
  270. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
  271. #define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
  272. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
  273. /* MMC boot config */
  274. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
  275. #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
  276. #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
  277. #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
  278. #define CONFIG_SPL_BOARD_INIT
  279. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  280. #define CONFIG_SPL_LIBDISK_SUPPORT
  281. #define CONFIG_SPL_I2C_SUPPORT
  282. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  283. #define CONFIG_SPL_MMC_SUPPORT
  284. #define CONFIG_SPL_FAT_SUPPORT
  285. #define CONFIG_SPL_SERIAL_SUPPORT
  286. #define CONFIG_SPL_POWER_SUPPORT
  287. #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
  288. #ifdef CONFIG_BOOT_ONENAND
  289. #define CONFIG_SPL_ONENAND_SUPPORT
  290. /* OneNAND boot config */
  291. #define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000
  292. #define CONFIG_SYS_ONENAND_PAGE_SIZE 2048
  293. #define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000
  294. #define CONFIG_SPL_ONENAND_LOAD_SIZE \
  295. (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
  296. #endif
  297. #ifdef CONFIG_BOOT_NAND
  298. #define CONFIG_SPL_NAND_SUPPORT
  299. #define CONFIG_SPL_NAND_BASE
  300. #define CONFIG_SPL_NAND_DRIVERS
  301. #define CONFIG_SPL_NAND_ECC
  302. /* NAND boot config */
  303. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  304. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  305. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  306. #define CONFIG_SYS_NAND_OOBSIZE 64
  307. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  308. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  309. #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
  310. 10, 11, 12, 13}
  311. #define CONFIG_SYS_NAND_ECCSIZE 512
  312. #define CONFIG_SYS_NAND_ECCBYTES 3
  313. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  314. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  315. #endif
  316. #endif /* __IGEP00X0_H */